Date: Tue, 31 Jan 2012 22:47:11 +0000 (UTC) From: Jack F Vogel <jfv@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r230848 - stable/8/sys/dev/e1000 Message-ID: <201201312247.q0VMlBA1058553@svn.freebsd.org>
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Author: jfv Date: Tue Jan 31 22:47:10 2012 New Revision: 230848 URL: http://svn.freebsd.org/changeset/base/230848 Log: MFC of e1000 drivers The following revs are merged: 212303,212304,213234,214363,214441,217556,219902,221505, 223676,226436,227309,228386,228387,228405,228415,228788, 228803,229606,229767,230023,230024,230742 Modified: stable/8/sys/dev/e1000/README stable/8/sys/dev/e1000/e1000_80003es2lan.c stable/8/sys/dev/e1000/e1000_80003es2lan.h stable/8/sys/dev/e1000/e1000_82540.c stable/8/sys/dev/e1000/e1000_82541.c stable/8/sys/dev/e1000/e1000_82543.c stable/8/sys/dev/e1000/e1000_82571.c stable/8/sys/dev/e1000/e1000_82575.c stable/8/sys/dev/e1000/e1000_82575.h stable/8/sys/dev/e1000/e1000_api.c stable/8/sys/dev/e1000/e1000_api.h stable/8/sys/dev/e1000/e1000_defines.h stable/8/sys/dev/e1000/e1000_hw.h stable/8/sys/dev/e1000/e1000_ich8lan.c stable/8/sys/dev/e1000/e1000_ich8lan.h stable/8/sys/dev/e1000/e1000_mac.c stable/8/sys/dev/e1000/e1000_nvm.c stable/8/sys/dev/e1000/e1000_nvm.h stable/8/sys/dev/e1000/e1000_osdep.c stable/8/sys/dev/e1000/e1000_phy.c stable/8/sys/dev/e1000/e1000_phy.h stable/8/sys/dev/e1000/e1000_regs.h stable/8/sys/dev/e1000/e1000_vf.c stable/8/sys/dev/e1000/if_em.c stable/8/sys/dev/e1000/if_em.h stable/8/sys/dev/e1000/if_igb.c stable/8/sys/dev/e1000/if_igb.h stable/8/sys/dev/e1000/if_lem.c stable/8/sys/dev/e1000/if_lem.h Directory Properties: stable/8/sys/dev/e1000/ (props changed) Modified: stable/8/sys/dev/e1000/README ============================================================================== --- stable/8/sys/dev/e1000/README Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/README Tue Jan 31 22:47:10 2012 (r230848) @@ -354,6 +354,7 @@ Known Limitations include: Planex FXG-08TE I-O Data ETG-SH8 + Netgear GS105v3 The driver can be compiled with the following changes: Modified: stable/8/sys/dev/e1000/e1000_80003es2lan.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_80003es2lan.c Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/e1000_80003es2lan.c Tue Jan 31 22:47:10 2012 (r230848) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2011, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -47,18 +47,18 @@ static void e1000_release_phy_80003es2la static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, - u32 offset, - u16 *data); + u32 offset, + u16 *data); static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, - u32 offset, - u16 data); + u32 offset, + u16 data); static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, - u16 words, u16 *data); + u16 words, u16 *data); static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, - u16 *duplex); + u16 *duplex); static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); @@ -68,9 +68,9 @@ static s32 e1000_cfg_kmrn_10_100_80003e static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, - u16 *data); + u16 *data); static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, - u16 data); + u16 data); static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); @@ -85,8 +85,8 @@ static void e1000_power_down_phy_copper_ static const u16 e1000_gg82563_cable_length_table[] = { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; #define GG82563_CABLE_LENGTH_TABLE_SIZE \ - (sizeof(e1000_gg82563_cable_length_table) / \ - sizeof(e1000_gg82563_cable_length_table[0])) + (sizeof(e1000_gg82563_cable_length_table) / \ + sizeof(e1000_gg82563_cable_length_table[0])) /** * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. @@ -100,34 +100,34 @@ static s32 e1000_init_phy_params_80003es DEBUGFUNC("e1000_init_phy_params_80003es2lan"); if (hw->phy.media_type != e1000_media_type_copper) { - phy->type = e1000_phy_none; + phy->type = e1000_phy_none; goto out; } else { phy->ops.power_up = e1000_power_up_phy_copper; phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; } - phy->addr = 1; - phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; - phy->reset_delay_us = 100; - phy->type = e1000_phy_gg82563; - - phy->ops.acquire = e1000_acquire_phy_80003es2lan; - phy->ops.check_polarity = e1000_check_polarity_m88; - phy->ops.check_reset_block = e1000_check_reset_block_generic; - phy->ops.commit = e1000_phy_sw_reset_generic; - phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; - phy->ops.get_info = e1000_get_phy_info_m88; - phy->ops.release = e1000_release_phy_80003es2lan; - phy->ops.reset = e1000_phy_hw_reset_generic; - phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 100; + phy->type = e1000_phy_gg82563; + + phy->ops.acquire = e1000_acquire_phy_80003es2lan; + phy->ops.check_polarity = e1000_check_polarity_m88; + phy->ops.check_reset_block = e1000_check_reset_block_generic; + phy->ops.commit = e1000_phy_sw_reset_generic; + phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; + phy->ops.get_info = e1000_get_phy_info_m88; + phy->ops.release = e1000_release_phy_80003es2lan; + phy->ops.reset = e1000_phy_hw_reset_generic; + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; - phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; - phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; - phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; + phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; + phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; + phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; - phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; + phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; /* This can only be done after all function pointers are setup. */ ret_val = e1000_get_phy_id(hw); @@ -154,19 +154,19 @@ static s32 e1000_init_nvm_params_80003es DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); - nvm->opcode_bits = 8; - nvm->delay_usec = 1; + nvm->opcode_bits = 8; + nvm->delay_usec = 1; switch (nvm->override) { case e1000_nvm_override_spi_large: - nvm->page_size = 32; + nvm->page_size = 32; nvm->address_bits = 16; break; case e1000_nvm_override_spi_small: - nvm->page_size = 8; + nvm->page_size = 8; nvm->address_bits = 8; break; default: - nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; break; } @@ -174,7 +174,7 @@ static s32 e1000_init_nvm_params_80003es nvm->type = e1000_nvm_eeprom_spi; size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> - E1000_EECD_SIZE_EX_SHIFT); + E1000_EECD_SIZE_EX_SHIFT); /* * Added to a constant, "size" becomes the left-shift value @@ -185,16 +185,16 @@ static s32 e1000_init_nvm_params_80003es /* EEPROM access above 16k is unsupported */ if (size > 14) size = 14; - nvm->word_size = 1 << size; + nvm->word_size = 1 << size; /* Function Pointers */ - nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; - nvm->ops.read = e1000_read_nvm_eerd; - nvm->ops.release = e1000_release_nvm_80003es2lan; - nvm->ops.update = e1000_update_nvm_checksum_generic; + nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; + nvm->ops.read = e1000_read_nvm_eerd; + nvm->ops.release = e1000_release_nvm_80003es2lan; + nvm->ops.update = e1000_update_nvm_checksum_generic; nvm->ops.valid_led_default = e1000_valid_led_default_generic; - nvm->ops.validate = e1000_validate_nvm_checksum_generic; - nvm->ops.write = e1000_write_nvm_80003es2lan; + nvm->ops.validate = e1000_validate_nvm_checksum_generic; + nvm->ops.write = e1000_write_nvm_80003es2lan; return E1000_SUCCESS; } @@ -215,13 +215,13 @@ static s32 e1000_init_mac_params_80003es hw->phy.media_type = e1000_media_type_internal_serdes; mac->ops.check_for_link = e1000_check_for_serdes_link_generic; mac->ops.setup_physical_interface = - e1000_setup_fiber_serdes_link_generic; + e1000_setup_fiber_serdes_link_generic; break; default: hw->phy.media_type = e1000_media_type_copper; mac->ops.check_for_link = e1000_check_for_copper_link_generic; mac->ops.setup_physical_interface = - e1000_setup_copper_link_80003es2lan; + e1000_setup_copper_link_80003es2lan; break; } @@ -234,9 +234,8 @@ static s32 e1000_init_mac_params_80003es /* FWSM register */ mac->has_fwsm = TRUE; /* ARC supported; valid only if manageability features are enabled. */ - mac->arc_subsystem_valid = - (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) - ? TRUE : FALSE; + mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) & + E1000_FWSM_MODE_MASK) ? TRUE : FALSE; /* Adaptive IFS not supported */ mac->adaptive_ifs = FALSE; @@ -330,7 +329,7 @@ static void e1000_release_phy_80003es2la } /** - * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register + * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register * @hw: pointer to the HW structure * * Acquire the semaphore to access the Kumeran interface. @@ -348,7 +347,7 @@ static s32 e1000_acquire_mac_csr_80003es } /** - * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register + * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register * @hw: pointer to the HW structure * * Release the semaphore used to access the Kumeran interface @@ -488,7 +487,7 @@ static void e1000_release_swfw_sync_8000 * Read the GG82563 PHY register. **/ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, - u32 offset, u16 *data) + u32 offset, u16 *data) { s32 ret_val; u32 page_select; @@ -538,14 +537,14 @@ static s32 e1000_read_phy_reg_gg82563_80 usec_delay(200); ret_val = e1000_read_phy_reg_mdic(hw, - MAX_PHY_REG_ADDRESS & offset, - data); + MAX_PHY_REG_ADDRESS & offset, + data); usec_delay(200); } else { ret_val = e1000_read_phy_reg_mdic(hw, - MAX_PHY_REG_ADDRESS & offset, - data); + MAX_PHY_REG_ADDRESS & offset, + data); } e1000_release_phy_80003es2lan(hw); @@ -563,7 +562,7 @@ out: * Write to the GG82563 PHY register. **/ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, - u32 offset, u16 data) + u32 offset, u16 data) { s32 ret_val; u32 page_select; @@ -613,14 +612,14 @@ static s32 e1000_write_phy_reg_gg82563_8 usec_delay(200); ret_val = e1000_write_phy_reg_mdic(hw, - MAX_PHY_REG_ADDRESS & offset, - data); + MAX_PHY_REG_ADDRESS & offset, + data); usec_delay(200); } else { ret_val = e1000_write_phy_reg_mdic(hw, - MAX_PHY_REG_ADDRESS & offset, - data); + MAX_PHY_REG_ADDRESS & offset, + data); } e1000_release_phy_80003es2lan(hw); @@ -639,7 +638,7 @@ out: * Write "words" of data to the ESB2 NVM. **/ static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, - u16 words, u16 *data) + u16 words, u16 *data) { DEBUGFUNC("e1000_write_nvm_80003es2lan"); @@ -729,11 +728,10 @@ static s32 e1000_phy_force_speed_duplex_ usec_delay(1); if (hw->phy.autoneg_wait_to_complete) { - DEBUGOUT("Waiting for forced speed/duplex link " - "on GG82563 phy.\n"); + DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, - 100000, &link); + 100000, &link); if (ret_val) goto out; @@ -749,12 +747,13 @@ static s32 e1000_phy_force_speed_duplex_ /* Try once more */ ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, - 100000, &link); + 100000, &link); if (ret_val) goto out; } - ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + &phy_data); if (ret_val) goto out; @@ -773,7 +772,8 @@ static s32 e1000_phy_force_speed_duplex_ * duplex. */ phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; - ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, + phy_data); out: return ret_val; @@ -826,21 +826,20 @@ out: * Retrieve the current speed and duplex configuration. **/ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, - u16 *duplex) + u16 *duplex) { s32 ret_val; DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); if (hw->phy.media_type == e1000_media_type_copper) { - ret_val = e1000_get_speed_and_duplex_copper_generic(hw, - speed, - duplex); + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, + duplex); hw->phy.ops.cfg_on_link_up(hw); } else { ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, - speed, - duplex); + speed, + duplex); } return ret_val; @@ -939,21 +938,21 @@ static s32 e1000_init_hw_80003es2lan(str /* Disable IBIST slave mode (far-end loopback) */ e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, - &kum_reg_data); + &kum_reg_data); kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, - kum_reg_data); + kum_reg_data); /* Set the transmit descriptor write-back policy */ reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | - E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); /* ...for both queues. */ reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | - E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; + E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); /* Enable retransmit on late collisions */ @@ -981,9 +980,9 @@ static s32 e1000_init_hw_80003es2lan(str hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; ret_val = e1000_read_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET >> - E1000_KMRNCTRLSTA_OFFSET_SHIFT, - &i); + E1000_KMRNCTRLSTA_OFFSET >> + E1000_KMRNCTRLSTA_OFFSET_SHIFT, + &i); if (!ret_val) { if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) @@ -1056,11 +1055,7 @@ static s32 e1000_copper_link_setup_gg825 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); - if (phy->reset_disable) - goto skip_reset; - - ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, - &data); + ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); if (ret_val) goto out; @@ -1068,8 +1063,7 @@ static s32 e1000_copper_link_setup_gg825 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ data |= GG82563_MSCR_TX_CLK_1000MBPS_25; - ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, - data); + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); if (ret_val) goto out; @@ -1122,7 +1116,6 @@ static s32 e1000_copper_link_setup_gg825 goto out; } -skip_reset: /* Bypass Rx and Tx FIFO's */ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, @@ -1132,14 +1125,12 @@ skip_reset: goto out; ret_val = e1000_read_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, - &data); + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data); if (ret_val) goto out; data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; ret_val = e1000_write_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, - data); + E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data); if (ret_val) goto out; @@ -1169,18 +1160,18 @@ skip_reset: /* Enable Electrical Idle on the PHY */ data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, - data); + data); if (ret_val) goto out; ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - &data); + &data); if (ret_val) goto out; data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - data); + data); if (ret_val) goto out; } @@ -1228,27 +1219,25 @@ static s32 e1000_setup_copper_link_80003 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), - 0xFFFF); + 0xFFFF); if (ret_val) goto out; ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), - ®_data); + ®_data); if (ret_val) goto out; reg_data |= 0x3F; ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), - reg_data); + reg_data); if (ret_val) goto out; ret_val = e1000_read_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, - ®_data); + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data); if (ret_val) goto out; reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; ret_val = e1000_write_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, - reg_data); + E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data); if (ret_val) goto out; @@ -1279,9 +1268,8 @@ static s32 e1000_cfg_on_link_up_80003es2 DEBUGFUNC("e1000_configure_on_link_up"); if (hw->phy.media_type == e1000_media_type_copper) { - ret_val = e1000_get_speed_and_duplex_copper_generic(hw, - &speed, - &duplex); + ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, + &duplex); if (ret_val) goto out; @@ -1314,8 +1302,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; ret_val = e1000_write_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, - reg_data); + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, + reg_data); if (ret_val) goto out; @@ -1327,12 +1315,12 @@ static s32 e1000_cfg_kmrn_10_100_80003es do { ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - ®_data); + ®_data); if (ret_val) goto out; ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - ®_data2); + ®_data2); if (ret_val) goto out; i++; @@ -1343,7 +1331,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es else reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + reg_data); out: return ret_val; @@ -1367,8 +1356,7 @@ static s32 e1000_cfg_kmrn_1000_80003es2l reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; ret_val = e1000_write_kmrn_reg_80003es2lan(hw, - E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, - reg_data); + E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); if (ret_val) goto out; @@ -1380,19 +1368,20 @@ static s32 e1000_cfg_kmrn_1000_80003es2l do { ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - ®_data); + ®_data); if (ret_val) goto out; ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, - ®_data2); + ®_data2); if (ret_val) goto out; i++; } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); + ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, + reg_data); out: return ret_val; @@ -1409,7 +1398,7 @@ out: * Release the semaphore before exiting. **/ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, - u16 *data) + u16 *data) { u32 kmrnctrlsta; s32 ret_val = E1000_SUCCESS; @@ -1421,8 +1410,9 @@ static s32 e1000_read_kmrn_reg_80003es2l goto out; kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & - E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; + E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); + E1000_WRITE_FLUSH(hw); usec_delay(2); @@ -1446,7 +1436,7 @@ out: * before exiting. **/ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, - u16 data) + u16 data) { u32 kmrnctrlsta; s32 ret_val = E1000_SUCCESS; @@ -1458,8 +1448,9 @@ static s32 e1000_write_kmrn_reg_80003es2 goto out; kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & - E1000_KMRNCTRLSTA_OFFSET) | data; + E1000_KMRNCTRLSTA_OFFSET) | data; E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); + E1000_WRITE_FLUSH(hw); usec_delay(2); Modified: stable/8/sys/dev/e1000/e1000_80003es2lan.h ============================================================================== --- stable/8/sys/dev/e1000/e1000_80003es2lan.h Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/e1000_80003es2lan.h Tue Jan 31 22:47:10 2012 (r230848) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2011, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,48 +35,47 @@ #ifndef _E1000_80003ES2LAN_H_ #define _E1000_80003ES2LAN_H_ -#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 -#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 -#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 -#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F - -#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 -#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 -#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 +#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 +#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 +#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 +#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F + +#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 +#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 +#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 -#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 -#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 +#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 +#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 -#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C -#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 +#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C +#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ -#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 +#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 -#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 -#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 +#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 +#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ -#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */ -#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 -#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ -#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ -#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ +#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */ +#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 +#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ +#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ +#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ /* PHY Specific Control Register 2 (Page 0, Register 26) */ -#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 - /* 1=Reverse Auto-Negotiation */ +#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Nego */ /* MAC Specific Control Register (Page 2, Register 21) */ /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ -#define GG82563_MSCR_TX_CLK_MASK 0x0007 -#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 -#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 -#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006 -#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 +#define GG82563_MSCR_TX_CLK_MASK 0x0007 +#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 +#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 +#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006 +#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 -#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ +#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ /* DSP Distance Register (Page 5, Register 26) */ /* @@ -86,19 +85,19 @@ * 3 = 110-140M * 4 = >140M */ -#define GG82563_DSPD_CABLE_LENGTH 0x0007 +#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* Kumeran Mode Control Register (Page 193, Register 16) */ -#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 +#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 /* Max number of times Kumeran read/write should be validated */ -#define GG82563_MAX_KMRN_RETRY 0x5 +#define GG82563_MAX_KMRN_RETRY 0x5 /* Power Management Control Register (Page 193, Register 20) */ -#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 - /* 1=Enable SERDES Electrical Idle */ +/* 1=Enable SERDES Electrical Idle */ +#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* In-Band Control Register (Page 194, Register 18) */ -#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ +#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ #endif Modified: stable/8/sys/dev/e1000/e1000_82540.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82540.c Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/e1000_82540.c Tue Jan 31 22:47:10 2012 (r230848) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2011, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -68,23 +68,23 @@ static s32 e1000_init_phy_params_82540(s struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; - phy->addr = 1; - phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; - phy->reset_delay_us = 10000; - phy->type = e1000_phy_m88; + phy->addr = 1; + phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; + phy->reset_delay_us = 10000; + phy->type = e1000_phy_m88; /* Function Pointers */ - phy->ops.check_polarity = e1000_check_polarity_m88; - phy->ops.commit = e1000_phy_sw_reset_generic; - phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; - phy->ops.get_cable_length = e1000_get_cable_length_m88; - phy->ops.get_cfg_done = e1000_get_cfg_done_generic; - phy->ops.read_reg = e1000_read_phy_reg_m88; - phy->ops.reset = e1000_phy_hw_reset_generic; - phy->ops.write_reg = e1000_write_phy_reg_m88; - phy->ops.get_info = e1000_get_phy_info_m88; - phy->ops.power_up = e1000_power_up_phy_copper; - phy->ops.power_down = e1000_power_down_phy_copper_82540; + phy->ops.check_polarity = e1000_check_polarity_m88; + phy->ops.commit = e1000_phy_sw_reset_generic; + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; + phy->ops.get_cable_length = e1000_get_cable_length_m88; + phy->ops.get_cfg_done = e1000_get_cfg_done_generic; + phy->ops.read_reg = e1000_read_phy_reg_m88; + phy->ops.reset = e1000_phy_hw_reset_generic; + phy->ops.write_reg = e1000_write_phy_reg_m88; + phy->ops.get_info = e1000_get_phy_info_m88; + phy->ops.power_up = e1000_power_up_phy_copper; + phy->ops.power_down = e1000_power_down_phy_copper_82540; ret_val = e1000_get_phy_id(hw); if (ret_val) @@ -121,32 +121,32 @@ static s32 e1000_init_nvm_params_82540(s DEBUGFUNC("e1000_init_nvm_params_82540"); - nvm->type = e1000_nvm_eeprom_microwire; - nvm->delay_usec = 50; - nvm->opcode_bits = 3; + nvm->type = e1000_nvm_eeprom_microwire; + nvm->delay_usec = 50; + nvm->opcode_bits = 3; switch (nvm->override) { case e1000_nvm_override_microwire_large: - nvm->address_bits = 8; - nvm->word_size = 256; + nvm->address_bits = 8; + nvm->word_size = 256; break; case e1000_nvm_override_microwire_small: - nvm->address_bits = 6; - nvm->word_size = 64; + nvm->address_bits = 6; + nvm->word_size = 64; break; default: - nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; - nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; + nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6; + nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64; break; } /* Function Pointers */ - nvm->ops.acquire = e1000_acquire_nvm_generic; - nvm->ops.read = e1000_read_nvm_microwire; - nvm->ops.release = e1000_release_nvm_generic; - nvm->ops.update = e1000_update_nvm_checksum_generic; - nvm->ops.valid_led_default = e1000_valid_led_default_generic; - nvm->ops.validate = e1000_validate_nvm_checksum_generic; - nvm->ops.write = e1000_write_nvm_microwire; + nvm->ops.acquire = e1000_acquire_nvm_generic; + nvm->ops.read = e1000_read_nvm_microwire; + nvm->ops.release = e1000_release_nvm_generic; + nvm->ops.update = e1000_update_nvm_checksum_generic; + nvm->ops.valid_led_default = e1000_valid_led_default_generic; + nvm->ops.validate = e1000_validate_nvm_checksum_generic; + nvm->ops.write = e1000_write_nvm_microwire; return E1000_SUCCESS; } @@ -198,9 +198,9 @@ static s32 e1000_init_mac_params_82540(s mac->ops.setup_link = e1000_setup_link_generic; /* physical interface setup */ mac->ops.setup_physical_interface = - (hw->phy.media_type == e1000_media_type_copper) - ? e1000_setup_copper_link_82540 - : e1000_setup_fiber_serdes_link_82540; + (hw->phy.media_type == e1000_media_type_copper) + ? e1000_setup_copper_link_82540 + : e1000_setup_fiber_serdes_link_82540; /* check for link */ switch (hw->phy.media_type) { case e1000_media_type_copper: @@ -219,9 +219,9 @@ static s32 e1000_init_mac_params_82540(s } /* link info */ mac->ops.get_link_up_info = - (hw->phy.media_type == e1000_media_type_copper) - ? e1000_get_speed_and_duplex_copper_generic - : e1000_get_speed_and_duplex_fiber_serdes_generic; + (hw->phy.media_type == e1000_media_type_copper) + ? e1000_get_speed_and_duplex_copper_generic + : e1000_get_speed_and_duplex_fiber_serdes_generic; /* multicast address update */ mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; /* writing VFTA */ @@ -374,7 +374,7 @@ static s32 e1000_init_hw_82540(struct e1 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | - E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_TXDCTL_FULL_TX_DESC_WB; E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); /* @@ -427,11 +427,13 @@ static s32 e1000_setup_copper_link_82540 if (hw->mac.type == e1000_82545_rev_3 || hw->mac.type == e1000_82546_rev_3) { - ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data); + ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, + &data); if (ret_val) goto out; data |= 0x00000008; - ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data); + ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, + data); if (ret_val) goto out; } @@ -508,9 +510,8 @@ static s32 e1000_adjust_serdes_amplitude if (nvm_data != NVM_RESERVED_WORD) { /* Adjust serdes output amplitude only. */ nvm_data &= NVM_SERDES_AMPLITUDE_MASK; - ret_val = hw->phy.ops.write_reg(hw, - M88E1000_PHY_EXT_CTRL, - nvm_data); + ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, + nvm_data); if (ret_val) goto out; } @@ -535,9 +536,8 @@ static s32 e1000_set_vco_speed_82540(str /* Set PHY register 30, page 5, bit 8 to 0 */ - ret_val = hw->phy.ops.read_reg(hw, - M88E1000_PHY_PAGE_SELECT, - &default_page); + ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT, + &default_page); if (ret_val) goto out; @@ -570,7 +570,7 @@ static s32 e1000_set_vco_speed_82540(str goto out; ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, - default_page); + default_page); out: return ret_val; @@ -587,7 +587,6 @@ out: **/ static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw) { - struct e1000_phy_info *phy = &hw->phy; s32 ret_val = E1000_SUCCESS; u16 nvm_data; @@ -604,20 +603,18 @@ static s32 e1000_set_phy_mode_82540(stru if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) { ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, - 0x000B); + 0x000B); if (ret_val) { ret_val = -E1000_ERR_PHY; goto out; } - ret_val = hw->phy.ops.write_reg(hw, - M88E1000_PHY_GEN_CONTROL, - 0x8104); + ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, + 0x8104); if (ret_val) { ret_val = -E1000_ERR_PHY; goto out; } - phy->reset_disable = FALSE; } out: Modified: stable/8/sys/dev/e1000/e1000_82541.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82541.c Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/e1000_82541.c Tue Jan 31 22:47:10 2012 (r230848) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation + Copyright (c) 2001-2011, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without @@ -300,7 +300,7 @@ void e1000_init_function_pointers_82541( **/ static s32 e1000_reset_hw_82541(struct e1000_hw *hw) { - u32 ledctl, ctrl, manc; + u32 ledctl, ctrl, icr, manc; DEBUGFUNC("e1000_reset_hw_82541"); @@ -364,7 +364,7 @@ static s32 e1000_reset_hw_82541(struct e E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); /* Clear any pending interrupt events. */ - E1000_READ_REG(hw, E1000_ICR); + icr = E1000_READ_REG(hw, E1000_ICR); return E1000_SUCCESS; } @@ -390,7 +390,7 @@ static s32 e1000_init_hw_82541(struct e1 DEBUGOUT("Error initializing identification LED\n"); /* This is not fatal and we should not stop init due to this */ } - + /* Storing the Speed Power Down value for later use */ ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, @@ -549,8 +549,6 @@ static s32 e1000_setup_copper_link_82541 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, E1000_CTRL, ctrl); - hw->phy.reset_disable = FALSE; - /* Earlier revs of the IGP phy require us to force MDI. */ if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { dev_spec->dsp_config = e1000_dsp_config_disabled; Modified: stable/8/sys/dev/e1000/e1000_82543.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82543.c Tue Jan 31 22:31:16 2012 (r230847) +++ stable/8/sys/dev/e1000/e1000_82543.c Tue Jan 31 22:47:10 2012 (r230848) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2010, Intel Corporation *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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