Date: Sat, 12 Feb 2011 00:07:40 +0000 (UTC) From: Jack F Vogel <jfv@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r218588 - head/sys/dev/e1000 Message-ID: <201102120007.p1C07en9078579@svn.freebsd.org>
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Author: jfv Date: Sat Feb 12 00:07:40 2011 New Revision: 218588 URL: http://svn.freebsd.org/changeset/base/218588 Log: Fix the shared code to be consistent with Intel-internal, and now build. Modified: head/sys/dev/e1000/e1000_80003es2lan.c head/sys/dev/e1000/e1000_80003es2lan.h head/sys/dev/e1000/e1000_82540.c head/sys/dev/e1000/e1000_82541.c head/sys/dev/e1000/e1000_82543.c head/sys/dev/e1000/e1000_82571.c head/sys/dev/e1000/e1000_api.h head/sys/dev/e1000/e1000_ich8lan.c head/sys/dev/e1000/e1000_ich8lan.h head/sys/dev/e1000/e1000_mac.h Modified: head/sys/dev/e1000/e1000_80003es2lan.c ============================================================================== --- head/sys/dev/e1000/e1000_80003es2lan.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_80003es2lan.c Sat Feb 12 00:07:40 2011 (r218588) @@ -82,8 +82,8 @@ static void e1000_power_down_phy_copper_ * with a lower bound at "index" and the upper bound at * "index + 5". */ -static const u16 e1000_gg82563_cable_length_table[] = - { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; +static const u16 e1000_gg82563_cable_length_table[] = { + 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; #define GG82563_CABLE_LENGTH_TABLE_SIZE \ (sizeof(e1000_gg82563_cable_length_table) / \ sizeof(e1000_gg82563_cable_length_table[0])) @@ -854,7 +854,7 @@ static s32 e1000_get_link_up_info_80003e **/ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) { - u32 ctrl, icr; + u32 ctrl; s32 ret_val; DEBUGFUNC("e1000_reset_hw_80003es2lan"); @@ -890,7 +890,7 @@ static s32 e1000_reset_hw_80003es2lan(st /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); ret_val = e1000_check_alt_mac_addr_generic(hw); @@ -909,6 +909,7 @@ static s32 e1000_init_hw_80003es2lan(str struct e1000_mac_info *mac = &hw->mac; u32 reg_data; s32 ret_val; + u16 kum_reg_data; u16 i; DEBUGFUNC("e1000_init_hw_80003es2lan"); @@ -936,6 +937,13 @@ static s32 e1000_init_hw_80003es2lan(str /* Setup link and flow control */ ret_val = mac->ops.setup_link(hw); + /* Disable IBIST slave mode (far-end loopback) */ + e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, + &kum_reg_data); + kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; + e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, + kum_reg_data); + /* Set the transmit descriptor write-back policy */ reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | Modified: head/sys/dev/e1000/e1000_80003es2lan.h ============================================================================== --- head/sys/dev/e1000/e1000_80003es2lan.h Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_80003es2lan.h Sat Feb 12 00:07:40 2011 (r218588) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2010, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without Modified: head/sys/dev/e1000/e1000_82540.c ============================================================================== --- head/sys/dev/e1000/e1000_82540.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_82540.c Sat Feb 12 00:07:40 2011 (r218588) @@ -269,7 +269,7 @@ void e1000_init_function_pointers_82540( **/ static s32 e1000_reset_hw_82540(struct e1000_hw *hw) { - u32 ctrl, icr, manc; + u32 ctrl, manc; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_reset_hw_82540"); @@ -314,7 +314,7 @@ static s32 e1000_reset_hw_82540(struct e E1000_WRITE_REG(hw, E1000_MANC, manc); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return ret_val; } Modified: head/sys/dev/e1000/e1000_82541.c ============================================================================== --- head/sys/dev/e1000/e1000_82541.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_82541.c Sat Feb 12 00:07:40 2011 (r218588) @@ -300,7 +300,7 @@ void e1000_init_function_pointers_82541( **/ static s32 e1000_reset_hw_82541(struct e1000_hw *hw) { - u32 ledctl, ctrl, icr, manc; + u32 ledctl, ctrl, manc; DEBUGFUNC("e1000_reset_hw_82541"); @@ -364,7 +364,7 @@ static s32 e1000_reset_hw_82541(struct e E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); /* Clear any pending interrupt events. */ - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return E1000_SUCCESS; } @@ -390,7 +390,7 @@ static s32 e1000_init_hw_82541(struct e1 DEBUGOUT("Error initializing identification LED\n"); /* This is not fatal and we should not stop init due to this */ } - + /* Storing the Speed Power Down value for later use */ ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, Modified: head/sys/dev/e1000/e1000_82543.c ============================================================================== --- head/sys/dev/e1000/e1000_82543.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_82543.c Sat Feb 12 00:07:40 2011 (r218588) @@ -901,7 +901,7 @@ static s32 e1000_phy_hw_reset_82543(stru **/ static s32 e1000_reset_hw_82543(struct e1000_hw *hw) { - u32 ctrl, icr; + u32 ctrl; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_reset_hw_82543"); @@ -943,7 +943,7 @@ static s32 e1000_reset_hw_82543(struct e /* Masking off and clearing any pending interrupts */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return ret_val; } Modified: head/sys/dev/e1000/e1000_82571.c ============================================================================== --- head/sys/dev/e1000/e1000_82571.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_82571.c Sat Feb 12 00:07:40 2011 (r218588) @@ -82,6 +82,10 @@ static s32 e1000_get_hw_semaphore_82573 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); +static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, + bool active); +static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, + bool active); static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); @@ -95,7 +99,6 @@ static void e1000_power_down_phy_copper_ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - struct e1000_dev_spec_82571 *dev_spec = &hw->dev_spec._82571; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_init_phy_params_82571"); @@ -129,16 +132,6 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_igp; phy->ops.acquire = e1000_get_hw_semaphore_82571; phy->ops.release = e1000_put_hw_semaphore_82571; - - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - - /* Verify PHY ID */ - if (phy->id != IGP01E1000_I_PHY_ID) { - ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; case e1000_82573: phy->type = e1000_phy_m88; @@ -152,20 +145,10 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_m88; phy->ops.acquire = e1000_get_hw_semaphore_82571; phy->ops.release = e1000_put_hw_semaphore_82571; - - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - - /* Verify PHY ID */ - if (phy->id != M88E1111_I_PHY_ID) { - ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; case e1000_82574: case e1000_82583: - E1000_MUTEX_INIT(&dev_spec->swflag_mutex); + E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); phy->type = e1000_phy_bm; phy->ops.get_cfg_done = e1000_get_cfg_done_generic; @@ -178,22 +161,46 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_bm2; phy->ops.acquire = e1000_get_hw_semaphore_82574; phy->ops.release = e1000_put_hw_semaphore_82574; + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + break; + } + + /* This can only be done after all function pointers are setup. */ + ret_val = e1000_get_phy_id_82571(hw); + if (ret_val) { + DEBUGOUT("Error getting PHY ID\n"); + goto out; + } - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - /* Verify PHY ID */ - if (phy->id != BME1000_E_PHY_ID_R2) { + /* Verify phy id */ + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + if (phy->id != IGP01E1000_I_PHY_ID) + ret_val = -E1000_ERR_PHY; + break; + case e1000_82573: + if (phy->id != M88E1111_I_PHY_ID) + ret_val = -E1000_ERR_PHY; + break; + case e1000_82574: + case e1000_82583: + if (phy->id != BME1000_E_PHY_ID_R2) ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; default: ret_val = -E1000_ERR_PHY; - goto out; break; } + if (ret_val) + DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); + out: return ret_val; } @@ -693,6 +700,62 @@ static void e1000_put_hw_semaphore_82574 } /** + * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D0 state according to the active flag. + * LPLU will not be activated unless the + * device autonegotiation advertisement meets standards of + * either 10 or 10/100 or 10/100/1000 at all duplexes. + * This is a function pointer entry point only called by + * PHY setup routines. + **/ +static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) +{ + u16 data = E1000_READ_REG(hw, E1000_POEMB); + + DEBUGFUNC("e1000_set_d0_lplu_state_82574"); + + if (active) + data |= E1000_PHY_CTRL_D0A_LPLU; + else + data &= ~E1000_PHY_CTRL_D0A_LPLU; + + E1000_WRITE_REG(hw, E1000_POEMB, data); + return E1000_SUCCESS; +} + +/** + * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * The low power link up (lplu) state is set to the power management level D3 + * when active is TRUE, else clear lplu for D3. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + **/ +static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) +{ + u16 data = E1000_READ_REG(hw, E1000_POEMB); + + DEBUGFUNC("e1000_set_d3_lplu_state_82574"); + + if (!active) { + data &= ~E1000_PHY_CTRL_NOND0A_LPLU; + } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || + (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= E1000_PHY_CTRL_NOND0A_LPLU; + } + + E1000_WRITE_REG(hw, E1000_POEMB, data); + return E1000_SUCCESS; +} + +/** * e1000_acquire_nvm_82571 - Request for access to the EEPROM * @hw: pointer to the HW structure * @@ -1039,7 +1102,7 @@ out: **/ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) { - u32 ctrl, ctrl_ext, icr; + u32 ctrl, ctrl_ext; s32 ret_val; DEBUGFUNC("e1000_reset_hw_82571"); @@ -1125,7 +1188,7 @@ static s32 e1000_reset_hw_82571(struct e /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); if (hw->mac.type == e1000_82571) { /* Install any alternate MAC address into RAR0 */ @@ -1336,7 +1399,7 @@ static void e1000_initialize_hw_bits_825 * apply workaround for hardware errata documented in errata * docs Fixes issue where some error prone or unreliable PCIe * completions are occurring, particularly with ASPM enabled. - * Without fix, issue can cause tx timeouts. + * Without fix, issue can cause Tx timeouts. */ reg = E1000_READ_REG(hw, E1000_GCR2); reg |= 1; @@ -1467,7 +1530,7 @@ bool e1000_check_phy_82574(struct e1000_ &receive_errors); if (ret_val) goto out; - if (receive_errors == E1000_RECEIVE_ERROR_MAX) { + if (receive_errors == E1000_RECEIVE_ERROR_MAX) { ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, &status_1kbt); if (ret_val) @@ -1510,6 +1573,7 @@ static s32 e1000_setup_link_82571(struct default: break; } + return e1000_setup_link_generic(hw); } @@ -1645,7 +1709,7 @@ static s32 e1000_check_for_serdes_link_8 * auto-negotiation in the TXCW register and disable * forced link in the Device Control register in an * attempt to auto-negotiate with our link partner. - * If the partner code word is null, stop forcing + * If the partner code word is null, stop forcing * and restart auto negotiation. */ if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { Modified: head/sys/dev/e1000/e1000_api.h ============================================================================== --- head/sys/dev/e1000/e1000_api.h Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_api.h Sat Feb 12 00:07:40 2011 (r218588) @@ -120,8 +120,6 @@ s32 e1000_mng_write_cmd_header(struct e s32 e1000_mng_write_dhcp_info(struct e1000_hw * hw, u8 *buffer, u16 length); u32 e1000_translate_register_82542(u32 reg); -s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); -s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); /* * TBI_ACCEPT macro definition: Modified: head/sys/dev/e1000/e1000_ich8lan.c ============================================================================== --- head/sys/dev/e1000/e1000_ich8lan.c Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_ich8lan.c Sat Feb 12 00:07:40 2011 (r218588) @@ -75,6 +75,9 @@ static void e1000_release_nvm_ich8lan(st static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); +static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, + u8 *mc_addr_list, + u32 mc_addr_count); static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); @@ -213,7 +216,8 @@ static s32 e1000_init_phy_params_pchlan( * the interconnect to PCIe mode. */ fwsm = E1000_READ_REG(hw, E1000_FWSM); - if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) { + if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && + !(hw->phy.ops.check_reset_block(hw))) { ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; @@ -540,6 +544,9 @@ static s32 e1000_init_mac_params_ich8lan case e1000_pch2lan: mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; mac->ops.rar_set = e1000_rar_set_pch2lan; + /* multicast address update for pch2 */ + mac->ops.update_mc_addr_list = + e1000_update_mc_addr_list_pch2lan; /* fall-through */ case e1000_pchlan: /* save PCH revision_id */ @@ -835,8 +842,13 @@ static void e1000_release_swflag_ich8lan DEBUGFUNC("e1000_release_swflag_ich8lan"); extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); - extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; - E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); + + if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { + extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; + E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); + } else { + DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n"); + } E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex); @@ -942,6 +954,34 @@ static void e1000_rar_set_pch2lan(struct } /** + * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses + * @hw: pointer to the HW structure + * @mc_addr_list: array of multicast addresses to program + * @mc_addr_count: number of multicast addresses to program + * + * Updates entire Multicast Table Array of the PCH2 MAC and PHY. + * The caller must have a packed mc_addr_list of multicast addresses. + **/ +static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, + u8 *mc_addr_list, + u32 mc_addr_count) +{ + int i; + + DEBUGFUNC("e1000_update_mc_addr_list_pch2lan"); + + e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count); + + for (i = 0; i < hw->mac.mta_reg_count; i++) { + hw->phy.ops.write_reg(hw, BM_MTA(i), + (u16)(hw->mac.mta_shadow[i] & 0xFFFF)); + hw->phy.ops.write_reg(hw, (BM_MTA(i) + 1), + (u16)((hw->mac.mta_shadow[i] >> 16) & + 0xFFFF)); + } +} + +/** * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked * @hw: pointer to the HW structure * @@ -1482,13 +1522,11 @@ static s32 e1000_hv_phy_workarounds_ich8 ret_val = hw->phy.ops.acquire(hw); if (ret_val) goto out; - ret_val = hw->phy.ops.read_reg_locked(hw, - PHY_REG(BM_PORT_CTRL_PAGE, 17), + ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG_REG, &phy_data); if (ret_val) goto release; - ret_val = hw->phy.ops.write_reg_locked(hw, - PHY_REG(BM_PORT_CTRL_PAGE, 17), + ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG_REG, phy_data & 0x00FF); release: hw->phy.ops.release(hw); @@ -1773,7 +1811,7 @@ out: /** * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware * @hw: pointer to the HW structure - * @gate: boolean set to TRUE to gate, FALSE to un-gate + * @gate: boolean set to TRUE to gate, FALSE to ungate * * Gate/ungate the automatic PHY configuration via hardware; perform * the configuration via software instead. @@ -1911,11 +1949,26 @@ static s32 e1000_post_phy_reset_ich8lan( /* Configure the LCD with the OEM bits in NVM */ ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE); - /* Ungate automatic PHY configuration on non-managed 82579 */ - if ((hw->mac.type == e1000_pch2lan) && - !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID)) { - msec_delay(10); - e1000_gate_hw_phy_config_ich8lan(hw, FALSE); + if (hw->mac.type == e1000_pch2lan) { + /* Ungate automatic PHY configuration on non-managed 82579 */ + if (!(E1000_READ_REG(hw, E1000_FWSM) & + E1000_ICH_FWSM_FW_VALID)) { + msec_delay(10); + e1000_gate_hw_phy_config_ich8lan(hw, FALSE); + } + + /* Set EEE LPI Update Timer to 200usec */ + ret_val = hw->phy.ops.acquire(hw); + if (ret_val) + goto out; + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, + I82579_LPI_UPDATE_TIMER); + if (ret_val) + goto release; + ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, + 0x1387); +release: + hw->phy.ops.release(hw); } out: @@ -2323,7 +2376,6 @@ static s32 e1000_flash_cycle_init_ich8la { union ich8_hws_flash_status hsfsts; s32 ret_val = -E1000_ERR_NVM; - s32 i = 0; DEBUGFUNC("e1000_flash_cycle_init_ich8lan"); @@ -2361,6 +2413,8 @@ static s32 e1000_flash_cycle_init_ich8la E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); ret_val = E1000_SUCCESS; } else { + s32 i; + /* * Otherwise poll for sometime so the current * cycle has a chance to end before giving up. @@ -3198,7 +3252,7 @@ static s32 e1000_reset_hw_ich8lan(struct { struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; u16 reg; - u32 ctrl, icr, kab; + u32 ctrl, kab; s32 ret_val; DEBUGFUNC("e1000_reset_hw_ich8lan"); @@ -3290,7 +3344,7 @@ static s32 e1000_reset_hw_ich8lan(struct E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); kab = E1000_READ_REG(hw, E1000_KABGTXD); kab |= E1000_KABGTXD_BGSQLBIAS; @@ -3665,7 +3719,7 @@ static s32 e1000_kmrn_lock_loss_workarou DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan"); - if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) + if (!dev_spec->kmrn_lock_loss_workaround_enabled) goto out; /* Modified: head/sys/dev/e1000/e1000_ich8lan.h ============================================================================== --- head/sys/dev/e1000/e1000_ich8lan.h Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_ich8lan.h Sat Feb 12 00:07:40 2011 (r218588) @@ -151,24 +151,24 @@ #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ -#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ +#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ #define HV_MUX_DATA_CTRL PHY_REG(776, 16) #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 -#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ -#define HV_SCC_LOWER PHY_REG(778, 17) -#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ -#define HV_ECOL_LOWER PHY_REG(778, 19) -#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ -#define HV_MCC_LOWER PHY_REG(778, 21) -#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ -#define HV_LATECOL_LOWER PHY_REG(778, 24) -#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ -#define HV_COLC_LOWER PHY_REG(778, 26) -#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ -#define HV_DC_LOWER PHY_REG(778, 28) -#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ -#define HV_TNCRS_LOWER PHY_REG(778, 30) +#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ +#define HV_SCC_LOWER PHY_REG(778, 17) +#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ +#define HV_ECOL_LOWER PHY_REG(778, 19) +#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ +#define HV_MCC_LOWER PHY_REG(778, 21) +#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ +#define HV_LATECOL_LOWER PHY_REG(778, 24) +#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ +#define HV_COLC_LOWER PHY_REG(778, 26) +#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ +#define HV_DC_LOWER PHY_REG(778, 28) +#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ +#define HV_TNCRS_LOWER PHY_REG(778, 30) #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ @@ -195,17 +195,22 @@ #define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */ /* KMRN Mode Control */ -#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) -#define HV_KMRN_MDIO_SLOW 0x0400 +#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) +#define HV_KMRN_MDIO_SLOW 0x0400 /* PHY Power Management Control */ -#define HV_PM_CTRL PHY_REG(770, 17) +#define HV_PM_CTRL PHY_REG(770, 17) #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ /* PHY Low Power Idle Control */ -#define I82579_LPI_CTRL PHY_REG(772, 20) -#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 +#define I82579_LPI_CTRL PHY_REG(772, 20) +#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 + +/* EMI Registers */ +#define I82579_EMI_ADDR 0x10 +#define I82579_EMI_DATA 0x11 +#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ /* * Additional interrupts need to be handled for ICH family: @@ -231,7 +236,7 @@ #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 /* Receive Address Initial CRC Calculation */ -#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) +#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state); Modified: head/sys/dev/e1000/e1000_mac.h ============================================================================== --- head/sys/dev/e1000/e1000_mac.h Fri Feb 11 23:08:34 2011 (r218587) +++ head/sys/dev/e1000/e1000_mac.h Sat Feb 12 00:07:40 2011 (r218588) @@ -52,6 +52,8 @@ s32 e1000_check_for_copper_link_generic s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw); s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw); s32 e1000_cleanup_led_generic(struct e1000_hw *hw); +s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); +s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw); s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw); s32 e1000_force_mac_fc_generic(struct e1000_hw *hw);
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