Date: Wed, 28 Nov 2018 09:22:54 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341123 - head/sys/dev/sfxge/common Message-ID: <201811280922.wAS9Msgv061870@repo.freebsd.org>
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Author: arybchik Date: Wed Nov 28 09:22:53 2018 New Revision: 341123 URL: https://svnweb.freebsd.org/changeset/base/341123 Log: sfxge(4): support Medford2 event timer semantics The event timer interface has changed for Medford2 - for details see bug66418 comment 9. Update the common code to use the new timer semantics for Medford2. Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18198 Modified: head/sys/dev/sfxge/common/ef10_ev.c head/sys/dev/sfxge/common/efx_regs_ef10.h Modified: head/sys/dev/sfxge/common/ef10_ev.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_ev.c Wed Nov 28 09:22:42 2018 (r341122) +++ head/sys/dev/sfxge/common/ef10_ev.c Wed Nov 28 09:22:53 2018 (r341123) @@ -732,9 +732,15 @@ ef10_ev_qmoderate( EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index, &dword, 0); } else { - EFX_POPULATE_DWORD_2(dword, + /* + * NOTE: The TMR_REL field introduced in Medford2 is + * ignored on earlier EF10 controllers. See bug66418 + * comment 9 for details. + */ + EFX_POPULATE_DWORD_3(dword, ERF_DZ_TC_TIMER_MODE, mode, - ERF_DZ_TC_TIMER_VAL, ticks); + ERF_DZ_TC_TIMER_VAL, ticks, + ERF_FZ_TC_TMR_REL_VAL, ticks); EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG, eep->ee_index, &dword, 0); } Modified: head/sys/dev/sfxge/common/efx_regs_ef10.h ============================================================================== --- head/sys/dev/sfxge/common/efx_regs_ef10.h Wed Nov 28 09:22:42 2018 (r341122) +++ head/sys/dev/sfxge/common/efx_regs_ef10.h Wed Nov 28 09:22:53 2018 (r341123) @@ -184,6 +184,8 @@ extern "C" { #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 +#define ERF_FZ_TC_TMR_REL_VAL_LBN 16 +#define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 #define ERF_FZ_TC_TIMER_MODE_LBN 14 #define ERF_FZ_TC_TIMER_MODE_WIDTH 2 #define ERF_FZ_TC_TIMER_VAL_LBN 0 @@ -202,6 +204,8 @@ extern "C" { #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 +/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ +/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */ /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ @@ -220,6 +224,8 @@ extern "C" { #define ER_DZ_EVQ_TMR_REG_RESET 0x0 +/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ +/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ #define ERF_DZ_TC_TIMER_MODE_LBN 14 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 #define ERF_DZ_TC_TIMER_VAL_LBN 0
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