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Date:      Fri, 24 Jun 2011 08:34:57 +0530
From:      "Jayachandran C." <c.jayachandran@gmail.com>
To:        Alan Cox <alc@rice.edu>
Cc:        src-committers@freebsd.org, Alan Cox <alc@freebsd.org>, svn-src-all@freebsd.org, "Bjoern A. Zeeb" <bz@freebsd.org>, svn-src-head@freebsd.org, Warner Losh <imp@bsdimp.com>
Subject:   Re: svn commit: r223464 - head/sys/vm
Message-ID:  <BANLkTinmJmMsabPEL4TLGm-XLeZ1QC-MxA@mail.gmail.com>
In-Reply-To: <4E039C0F.10505@rice.edu>
References:  <201106230524.p5N5O0Rs084548@svn.freebsd.org> <31243267-5FE1-4104-9B77-4F3EAAD4523B@FreeBSD.org> <B790D7A9-CDE6-482A-BF58-686CA5FF9667@bsdimp.com> <4E039C0F.10505@rice.edu>

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On Fri, Jun 24, 2011 at 1:33 AM, Alan Cox <alc@rice.edu> wrote:
> On 6/23/2011 1:30 PM, Warner Losh wrote:
>>
>> On Jun 23, 2011, at 2:17 AM, Bjoern A. Zeeb wrote:
>>
>>> On Jun 23, 2011, at 5:24 AM, Alan Cox wrote:
>>>
>>>> Author: alc
>>>> Date: Thu Jun 23 05:23:59 2011
>>>> New Revision: 223464
>>>> URL: http://svn.freebsd.org/changeset/base/223464
>>>>
>>>> Log:
>>>> Revert to using the page queues lock in vm_page_clear_dirty_mask() on
>>>> MIPS.  (At present, although atomic_clear_char() is defined by atomic.h
>>>> on MIPS, it is not actually implemented by support.S.)
>>>
>>> Thanks,
>>> and good catch on the atomics even if not planned, just in time for 9.0:)
>>
>> Yea, there's some work there to fix them...  Not sure we can even fix some
>> of them atomically...
>>
>
> I'm not sure that I understand what you mean by the second statement.  Can
> you elaborate?  The 8- and 16-bit operations should be no less "atomic" than
> the 32- and 64-bit operations.  In general, regardless of the size of the
> operation, the "sc" instruction may fail and the whole operation has to be
> restarted if another processor (or I/O device) performs a concurrent, cache
> coherent store to the same location (or even cache line) as the "ll" and
> "sc" instructions are operating on.  On the other hand, if the "sc"
> instruction succeeds, whether you used it to change all of the 32 bits or
> just 8 of the 32 bits, it should appear as an atomic change to any other
> processor.

I will try out an implementation and see if this works on XLR, if so
this is something we can add to support.S

JC.


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