Date: Tue, 10 Nov 2015 13:20:21 +0000 (UTC) From: Svatopluk Kraus <skra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290656 - head/sys/arm/include Message-ID: <201511101320.tAADKLVw039989@repo.freebsd.org>
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Author: skra Date: Tue Nov 10 13:20:21 2015 New Revision: 290656 URL: https://svnweb.freebsd.org/changeset/base/290656 Log: Fix cp15 PAR definition and function. While here, add cp15 ATS1CPW function which checks an address for privileged (PL1) write access. The function is inlined so it does not bring any cost, but makes function set for checking privileged access complete. Approved by: kib (mentor) Modified: head/sys/arm/include/cpu-v6.h head/sys/arm/include/sysreg.h Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Tue Nov 10 13:15:34 2015 (r290655) +++ head/sys/arm/include/cpu-v6.h Tue Nov 10 13:20:21 2015 (r290656) @@ -156,8 +156,9 @@ _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0)) _RF0(cp15_actlr_get, CP15_ACTLR(%0)) _WF1(cp15_actlr_set, CP15_ACTLR(%0)) #if __ARM_ARCH >= 6 -_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)); -_RF0(cp15_par_get, CP15_PAR); +_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)) +_WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0)) +_RF0(cp15_par_get, CP15_PAR(%0)) _RF0(cp15_sctlr_get, CP15_SCTLR(%0)) #endif Modified: head/sys/arm/include/sysreg.h ============================================================================== --- head/sys/arm/include/sysreg.h Tue Nov 10 13:15:34 2015 (r290655) +++ head/sys/arm/include/sysreg.h Tue Nov 10 13:20:21 2015 (r290656) @@ -130,7 +130,7 @@ #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ #endif -#define CP15_PAR p15, 0, r0, c7, c4, 0 /* Physical Address Register */ +#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ #define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */
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