Date: Wed, 20 Sep 2017 18:30:37 +0000 (UTC) From: Conrad Meyer <cem@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323822 - in head/sys/x86: include x86 Message-ID: <201709201830.v8KIUbJ0083385@repo.freebsd.org>
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Author: cem Date: Wed Sep 20 18:30:37 2017 New Revision: 323822 URL: https://svnweb.freebsd.org/changeset/base/323822 Log: x86: Decode AMD "Extended Feature Extensions ID EBX" bits In particular, this determines CPU support for the CLZERO instruction. (No, I am not making this name up.) Sponsored by: Dell EMC Isilon Modified: head/sys/x86/include/specialreg.h head/sys/x86/include/x86_var.h head/sys/x86/x86/identcpu.c Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Wed Sep 20 18:04:28 2017 (r323821) +++ head/sys/x86/include/specialreg.h Wed Sep 20 18:30:37 2017 (r323822) @@ -331,6 +331,13 @@ #define AMDPM_CPB 0x00000200 /* + * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) + */ +#define AMDFEID_CLZERO 0x00000001 +#define AMDFEID_IRPERF 0x00000002 +#define AMDFEID_XSAVEERPTR 0x00000004 + +/* * AMD extended function 8000_0008h ecx info */ #define AMDID_CMP_CORES 0x000000ff Modified: head/sys/x86/include/x86_var.h ============================================================================== --- head/sys/x86/include/x86_var.h Wed Sep 20 18:04:28 2017 (r323821) +++ head/sys/x86/include/x86_var.h Wed Sep 20 18:30:37 2017 (r323822) @@ -46,6 +46,7 @@ extern u_int amd_feature; extern u_int amd_feature2; extern u_int amd_rascap; extern u_int amd_pminfo; +extern u_int amd_extended_feature_extensions; extern u_int via_feature_rng; extern u_int via_feature_xcrypt; extern u_int cpu_clflush_line_size; Modified: head/sys/x86/x86/identcpu.c ============================================================================== --- head/sys/x86/x86/identcpu.c Wed Sep 20 18:04:28 2017 (r323821) +++ head/sys/x86/x86/identcpu.c Wed Sep 20 18:30:37 2017 (r323822) @@ -93,6 +93,7 @@ u_int amd_feature; /* AMD feature flags */ u_int amd_feature2; /* AMD feature flags */ u_int amd_rascap; /* AMD RAS capabilities */ u_int amd_pminfo; /* AMD advanced power management info */ +u_int amd_extended_feature_extensions; u_int via_feature_rng; /* VIA RNG features */ u_int via_feature_xcrypt; /* VIA ACE features */ u_int cpu_high; /* Highest arg to CPUID */ @@ -992,6 +993,16 @@ printcpuinfo(void) } } + if (amd_extended_feature_extensions != 0) { + printf("\n " + "AMD Extended Feature Extensions ID EBX=" + "0x%b", amd_extended_feature_extensions, + "\020" + "\001CLZERO" + "\002IRPerf" + "\003XSaveErPtr"); + } + if (via_feature_rng != 0 || via_feature_xcrypt != 0) print_via_padlock_info(); @@ -1468,6 +1479,7 @@ finishidentcpu(void) if (cpu_exthigh >= 0x80000008) { do_cpuid(0x80000008, regs); cpu_maxphyaddr = regs[0] & 0xff; + amd_extended_feature_extensions = regs[1]; cpu_procinfo2 = regs[2]; } else { cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
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