Date: Thu, 20 Feb 2014 21:56:16 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r262261 - in projects/clang-sparc64/contrib/llvm: include/llvm/MC include/llvm/Object include/llvm/Support lib/CodeGen/AsmPrinter lib/CodeGen/SelectionDAG lib/MC lib/Object lib/Target/A... Message-ID: <201402202156.s1KLuGIf074348@svn.freebsd.org>
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Author: dim Date: Thu Feb 20 21:56:15 2014 New Revision: 262261 URL: http://svnweb.freebsd.org/changeset/base/262261 Log: Import a whole bunch of llvm trunk commits to enable self-hosting clang 3.4 on Sparc64 (commit descriptions left out for brevity): r196755 r198028 r198029 r198030 r198145 r198149 r198157 r198565 r199186 r199187 r198280 r198281 r198286 r198480 r198484 r198533 r198567 r198580 r198591 r198592 r198658 r198681 r198738 r198739 r198740 r198893 r198909 r198910 r199014 r199024 r199028 r199031 r199033 r199061 r199775 r199781 r199786 r199940 r199974 r199975 r199977 r200103 r200104 r200112 r200130 r200131 r200141 r200282 r200368 r200373 r200376 r200509 r200617 r200960 r200961 r200962 r200963 r200965 Submitted by: rdivacky Added: projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/AsmParser/ projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/Disassembler/ projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/InstPrinter/ projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcMCInstLower.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcTargetObjectFile.h (contents, props changed) projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcTargetStreamer.h (contents, props changed) Modified: projects/clang-sparc64/contrib/llvm/include/llvm/MC/MCAsmInfo.h projects/clang-sparc64/contrib/llvm/include/llvm/Object/ELFObjectFile.h projects/clang-sparc64/contrib/llvm/include/llvm/Support/ELF.h projects/clang-sparc64/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp projects/clang-sparc64/contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp projects/clang-sparc64/contrib/llvm/lib/MC/MCObjectFileInfo.cpp projects/clang-sparc64/contrib/llvm/lib/Object/ELF.cpp projects/clang-sparc64/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/Sparc.h projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/Sparc.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcCallingConv.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcISelLowering.h projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcInstrFormats.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.td projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcJITInfo.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcRelocations.h projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcSubtarget.cpp projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/SparcSubtarget.h Modified: projects/clang-sparc64/contrib/llvm/include/llvm/MC/MCAsmInfo.h ============================================================================== --- projects/clang-sparc64/contrib/llvm/include/llvm/MC/MCAsmInfo.h Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/include/llvm/MC/MCAsmInfo.h Thu Feb 20 21:56:15 2014 (r262261) @@ -371,7 +371,7 @@ namespace llvm { unsigned Encoding, MCStreamer &Streamer) const; - const MCExpr * + virtual const MCExpr * getExprForFDESymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const; Modified: projects/clang-sparc64/contrib/llvm/include/llvm/Object/ELFObjectFile.h ============================================================================== --- projects/clang-sparc64/contrib/llvm/include/llvm/Object/ELFObjectFile.h Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/include/llvm/Object/ELFObjectFile.h Thu Feb 20 21:56:15 2014 (r262261) @@ -922,6 +922,9 @@ StringRef ELFObjectFile<ELFT>::getFileFo return "ELF32-mips"; case ELF::EM_PPC: return "ELF32-ppc"; + case ELF::EM_SPARC: + case ELF::EM_SPARC32PLUS: + return "ELF32-sparc"; default: return "ELF32-unknown"; } @@ -937,6 +940,8 @@ StringRef ELFObjectFile<ELFT>::getFileFo return "ELF64-ppc64"; case ELF::EM_S390: return "ELF64-s390"; + case ELF::EM_SPARCV9: + return "ELF64-sparc"; default: return "ELF64-unknown"; } @@ -967,6 +972,13 @@ unsigned ELFObjectFile<ELFT>::getArch() : Triple::ppc64; case ELF::EM_S390: return Triple::systemz; + + case ELF::EM_SPARC: + case ELF::EM_SPARC32PLUS: + return Triple::sparc; + case ELF::EM_SPARCV9: + return Triple::sparcv9; + default: return Triple::UnknownArch; } Modified: projects/clang-sparc64/contrib/llvm/include/llvm/Support/ELF.h ============================================================================== --- projects/clang-sparc64/contrib/llvm/include/llvm/Support/ELF.h Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/include/llvm/Support/ELF.h Thu Feb 20 21:56:15 2014 (r262261) @@ -1087,6 +1087,94 @@ enum { R_390_IRELATIVE = 61 }; +// ELF Relocation type for Sparc. +enum { + R_SPARC_NONE = 0, + R_SPARC_8 = 1, + R_SPARC_16 = 2, + R_SPARC_32 = 3, + R_SPARC_DISP8 = 4, + R_SPARC_DISP16 = 5, + R_SPARC_DISP32 = 6, + R_SPARC_WDISP30 = 7, + R_SPARC_WDISP22 = 8, + R_SPARC_HI22 = 9, + R_SPARC_22 = 10, + R_SPARC_13 = 11, + R_SPARC_LO10 = 12, + R_SPARC_GOT10 = 13, + R_SPARC_GOT13 = 14, + R_SPARC_GOT22 = 15, + R_SPARC_PC10 = 16, + R_SPARC_PC22 = 17, + R_SPARC_WPLT30 = 18, + R_SPARC_COPY = 19, + R_SPARC_GLOB_DAT = 20, + R_SPARC_JMP_SLOT = 21, + R_SPARC_RELATIVE = 22, + R_SPARC_UA32 = 23, + R_SPARC_PLT32 = 24, + R_SPARC_HIPLT22 = 25, + R_SPARC_LOPLT10 = 26, + R_SPARC_PCPLT32 = 27, + R_SPARC_PCPLT22 = 28, + R_SPARC_PCPLT10 = 29, + R_SPARC_10 = 30, + R_SPARC_11 = 31, + R_SPARC_64 = 32, + R_SPARC_OLO10 = 33, + R_SPARC_HH22 = 34, + R_SPARC_HM10 = 35, + R_SPARC_LM22 = 36, + R_SPARC_PC_HH22 = 37, + R_SPARC_PC_HM10 = 38, + R_SPARC_PC_LM22 = 39, + R_SPARC_WDISP16 = 40, + R_SPARC_WDISP19 = 41, + R_SPARC_7 = 43, + R_SPARC_5 = 44, + R_SPARC_6 = 45, + R_SPARC_DISP64 = 46, + R_SPARC_PLT64 = 47, + R_SPARC_HIX22 = 48, + R_SPARC_LOX10 = 49, + R_SPARC_H44 = 50, + R_SPARC_M44 = 51, + R_SPARC_L44 = 52, + R_SPARC_REGISTER = 53, + R_SPARC_UA64 = 54, + R_SPARC_UA16 = 55, + R_SPARC_TLS_GD_HI22 = 56, + R_SPARC_TLS_GD_LO10 = 57, + R_SPARC_TLS_GD_ADD = 58, + R_SPARC_TLS_GD_CALL = 59, + R_SPARC_TLS_LDM_HI22 = 60, + R_SPARC_TLS_LDM_LO10 = 61, + R_SPARC_TLS_LDM_ADD = 62, + R_SPARC_TLS_LDM_CALL = 63, + R_SPARC_TLS_LDO_HIX22 = 64, + R_SPARC_TLS_LDO_LOX10 = 65, + R_SPARC_TLS_LDO_ADD = 66, + R_SPARC_TLS_IE_HI22 = 67, + R_SPARC_TLS_IE_LO10 = 68, + R_SPARC_TLS_IE_LD = 69, + R_SPARC_TLS_IE_LDX = 70, + R_SPARC_TLS_IE_ADD = 71, + R_SPARC_TLS_LE_HIX22 = 72, + R_SPARC_TLS_LE_LOX10 = 73, + R_SPARC_TLS_DTPMOD32 = 74, + R_SPARC_TLS_DTPMOD64 = 75, + R_SPARC_TLS_DTPOFF32 = 76, + R_SPARC_TLS_DTPOFF64 = 77, + R_SPARC_TLS_TPOFF32 = 78, + R_SPARC_TLS_TPOFF64 = 79, + R_SPARC_GOTDATA_HIX22 = 80, + R_SPARC_GOTDATA_LOX22 = 81, + R_SPARC_GOTDATA_OP_HIX22 = 82, + R_SPARC_GOTDATA_OP_LOX22 = 83, + R_SPARC_GOTDATA_OP = 84 +}; + // Section header. struct Elf32_Shdr { Elf32_Word sh_name; // Section name (index into string table) Modified: projects/clang-sparc64/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp ============================================================================== --- projects/clang-sparc64/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBundle.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -2221,14 +2222,13 @@ isBlockOnlyReachableByFallthrough(const if (!MI.isBranch() || MI.isIndirectBranch()) return false; - // If we are the operands of one of the branches, this is not - // a fall through. - for (MachineInstr::mop_iterator OI = MI.operands_begin(), - OE = MI.operands_end(); OI != OE; ++OI) { - const MachineOperand& OP = *OI; - if (OP.isJTI()) + // If we are the operands of one of the branches, this is not a fall + // through. Note that targets with delay slots will usually bundle + // terminators with the delay slot instruction. + for (ConstMIBundleOperands OP(&MI); OP.isValid(); ++OP) { + if (OP->isJTI()) return false; - if (OP.isMBB() && OP.getMBB() == MBB) + if (OP->isMBB() && OP->getMBB() == MBB) return false; } } Modified: projects/clang-sparc64/contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp ============================================================================== --- projects/clang-sparc64/contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -220,10 +220,19 @@ void InstrEmitter::CreateVirtualRegister unsigned VRBase = 0; const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); - // If the register class is unknown for the given definition, then try to - // infer one from the value type. - if (!RC && i < NumResults) - RC = TLI->getRegClassFor(Node->getSimpleValueType(i)); + // Always let the value type influence the used register class. The + // constraints on the instruction may be too lax to represent the value + // type correctly. For example, a 64-bit float (X86::FR64) can't live in + // the 32-bit float super-class (X86::FR32). + if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { + const TargetRegisterClass *VTRC = + TLI->getRegClassFor(Node->getSimpleValueType(i)); + if (RC) + VTRC = TRI->getCommonSubClass(RC, VTRC); + if (VTRC) + RC = VTRC; + } + if (II.OpInfo[i].isOptionalDef()) { // Optional def must be a physical register. unsigned NumResults = CountResults(Node); Modified: projects/clang-sparc64/contrib/llvm/lib/MC/MCObjectFileInfo.cpp ============================================================================== --- projects/clang-sparc64/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -310,6 +310,33 @@ void MCObjectFileInfo::InitELFMCObjectFi FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8; TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8; + } else if (T.getArch() == Triple::sparc) { + if (RelocM == Reloc::PIC_) { + LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + dwarf::DW_EH_PE_sdata4; + FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + dwarf::DW_EH_PE_sdata4; + } else { + LSDAEncoding = dwarf::DW_EH_PE_absptr; + PersonalityEncoding = dwarf::DW_EH_PE_absptr; + FDEEncoding = dwarf::DW_EH_PE_udata4; + TTypeEncoding = dwarf::DW_EH_PE_absptr; + } + } else if (T.getArch() == Triple::sparcv9) { + LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + if (RelocM == Reloc::PIC_) { + PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + dwarf::DW_EH_PE_sdata4; + FDEEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4; + TTypeEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | + dwarf::DW_EH_PE_sdata4; + } else { + PersonalityEncoding = dwarf::DW_EH_PE_absptr; + FDEEncoding = dwarf::DW_EH_PE_udata4; + TTypeEncoding = dwarf::DW_EH_PE_absptr; + } } else if (T.getArch() == Triple::systemz) { // All currently-defined code models guarantee that 4-byte PC-relative // values will be in range. Modified: projects/clang-sparc64/contrib/llvm/lib/Object/ELF.cpp ============================================================================== --- projects/clang-sparc64/contrib/llvm/lib/Object/ELF.cpp Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/lib/Object/ELF.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -702,6 +702,98 @@ StringRef getELFRelocationTypeName(uint3 break; } break; + case ELF::EM_SPARC: + case ELF::EM_SPARC32PLUS: + case ELF::EM_SPARCV9: + switch (Type) { + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_NONE); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_8); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_16); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_DISP8); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_DISP16); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_DISP32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_WDISP30); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_WDISP22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_HI22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_13); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_LO10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOT10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOT13); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOT22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PC10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PC22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_WPLT30); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_COPY); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GLOB_DAT); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_JMP_SLOT); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_RELATIVE); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_UA32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PLT32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_HIPLT22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_LOPLT10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PCPLT32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PCPLT22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PCPLT10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_11); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_OLO10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_HH22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_HM10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_LM22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PC_HH22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PC_HM10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PC_LM22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_WDISP16); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_WDISP19); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_7); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_5); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_6); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_DISP64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_PLT64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_HIX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_LOX10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_H44); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_M44); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_L44); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_REGISTER); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_UA64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_UA16); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_GD_HI22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_GD_LO10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_GD_ADD); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_GD_CALL); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDM_HI22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDM_LO10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDM_ADD); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDM_CALL); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDO_HIX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDO_LOX10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LDO_ADD); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_IE_HI22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_IE_LO10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_IE_LD); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_IE_LDX); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_IE_ADD); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LE_HIX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_LE_LOX10); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_DTPMOD32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_DTPMOD64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_DTPOFF32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_DTPOFF64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_TPOFF32); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_TLS_TPOFF64); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOTDATA_HIX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOTDATA_LOX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOTDATA_OP_HIX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOTDATA_OP_LOX22); + LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_SPARC_GOTDATA_OP); + default: + break; + } + break; default: break; } Modified: projects/clang-sparc64/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp ============================================================================== --- projects/clang-sparc64/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 20 21:52:39 2014 (r262260) +++ projects/clang-sparc64/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -156,7 +156,7 @@ void ARMTargetLowering::addDRTypeForNEON } void ARMTargetLowering::addQRTypeForNEON(MVT VT) { - addRegisterClass(VT, &ARM::QPRRegClass); + addRegisterClass(VT, &ARM::DPairRegClass); addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); } Added: projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/clang-sparc64/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Thu Feb 20 21:56:15 2014 (r262261) @@ -0,0 +1,828 @@ +//===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/SparcMCTargetDesc.h" +#include "MCTargetDesc/SparcMCExpr.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetAsmParser.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +// The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target +// namespace. But SPARC backend uses "SP" as its namespace. +namespace llvm { + namespace Sparc { + using namespace SP; + } +} + +namespace { +class SparcOperand; +class SparcAsmParser : public MCTargetAsmParser { + + MCSubtargetInfo &STI; + MCAsmParser &Parser; + + /// @name Auto-generated Match Functions + /// { + +#define GET_ASSEMBLER_HEADER +#include "SparcGenAsmMatcher.inc" + + /// } + + // public interface of the MCTargetAsmParser. + bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, + SmallVectorImpl<MCParsedAsmOperand*> &Operands, + MCStreamer &Out, unsigned &ErrorInfo, + bool MatchingInlineAsm); + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); + bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, + SmallVectorImpl<MCParsedAsmOperand*> &Operands); + bool ParseDirective(AsmToken DirectiveID); + + virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, + unsigned Kind); + + // Custom parse functions for Sparc specific operands. + OperandMatchResultTy + parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); + + OperandMatchResultTy + parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, + StringRef Name); + + OperandMatchResultTy + parseSparcAsmOperand(SparcOperand *&Operand); + + // returns true if Tok is matched to a register and returns register in RegNo. + bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, + unsigned &RegKind); + + bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); + +public: + SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, + const MCInstrInfo &MII) + : MCTargetAsmParser(), STI(sti), Parser(parser) { + // Initialize the set of available features. + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + } + +}; + + static unsigned IntRegs[32] = { + Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3, + Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7, + Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3, + Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7, + Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3, + Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7, + Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3, + Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 }; + + static unsigned FloatRegs[32] = { + Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3, + Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7, + Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11, + Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15, + Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19, + Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23, + Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27, + Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 }; + + static unsigned DoubleRegs[32] = { + Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3, + Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7, + Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9, + Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15, + Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19, + Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23, + Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27, + Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 }; + + static unsigned QuadFPRegs[32] = { + Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3, + Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7, + Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11, + Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 }; + + +/// SparcOperand - Instances of this class represent a parsed Sparc machine +/// instruction. +class SparcOperand : public MCParsedAsmOperand { +public: + enum RegisterKind { + rk_None, + rk_IntReg, + rk_FloatReg, + rk_DoubleReg, + rk_QuadReg, + rk_CCReg, + rk_Y + }; +private: + enum KindTy { + k_Token, + k_Register, + k_Immediate, + k_MemoryReg, + k_MemoryImm + } Kind; + + SMLoc StartLoc, EndLoc; + + SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} + + struct Token { + const char *Data; + unsigned Length; + }; + + struct RegOp { + unsigned RegNum; + RegisterKind Kind; + }; + + struct ImmOp { + const MCExpr *Val; + }; + + struct MemOp { + unsigned Base; + unsigned OffsetReg; + const MCExpr *Off; + }; + + union { + struct Token Tok; + struct RegOp Reg; + struct ImmOp Imm; + struct MemOp Mem; + }; +public: + bool isToken() const { return Kind == k_Token; } + bool isReg() const { return Kind == k_Register; } + bool isImm() const { return Kind == k_Immediate; } + bool isMem() const { return isMEMrr() || isMEMri(); } + bool isMEMrr() const { return Kind == k_MemoryReg; } + bool isMEMri() const { return Kind == k_MemoryImm; } + + bool isFloatReg() const { + return (Kind == k_Register && Reg.Kind == rk_FloatReg); + } + + bool isFloatOrDoubleReg() const { + return (Kind == k_Register && (Reg.Kind == rk_FloatReg + || Reg.Kind == rk_DoubleReg)); + } + + + StringRef getToken() const { + assert(Kind == k_Token && "Invalid access!"); + return StringRef(Tok.Data, Tok.Length); + } + + unsigned getReg() const { + assert((Kind == k_Register) && "Invalid access!"); + return Reg.RegNum; + } + + const MCExpr *getImm() const { + assert((Kind == k_Immediate) && "Invalid access!"); + return Imm.Val; + } + + unsigned getMemBase() const { + assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!"); + return Mem.Base; + } + + unsigned getMemOffsetReg() const { + assert((Kind == k_MemoryReg) && "Invalid access!"); + return Mem.OffsetReg; + } + + const MCExpr *getMemOff() const { + assert((Kind == k_MemoryImm) && "Invalid access!"); + return Mem.Off; + } + + /// getStartLoc - Get the location of the first token of this operand. + SMLoc getStartLoc() const { + return StartLoc; + } + /// getEndLoc - Get the location of the last token of this operand. + SMLoc getEndLoc() const { + return EndLoc; + } + + virtual void print(raw_ostream &OS) const { + switch (Kind) { + case k_Token: OS << "Token: " << getToken() << "\n"; break; + case k_Register: OS << "Reg: #" << getReg() << "\n"; break; + case k_Immediate: OS << "Imm: " << getImm() << "\n"; break; + case k_MemoryReg: OS << "Mem: " << getMemBase() << "+" + << getMemOffsetReg() << "\n"; break; + case k_MemoryImm: assert(getMemOff() != 0); + OS << "Mem: " << getMemBase() + << "+" << *getMemOff() + << "\n"; break; + } + } + + void addRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(getReg())); + } + + void addImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCExpr *Expr = getImm(); + addExpr(Inst, Expr); + } + + void addExpr(MCInst &Inst, const MCExpr *Expr) const{ + // Add as immediate when possible. Null MCExpr = 0. + if (Expr == 0) + Inst.addOperand(MCOperand::CreateImm(0)); + else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) + Inst.addOperand(MCOperand::CreateImm(CE->getValue())); + else + Inst.addOperand(MCOperand::CreateExpr(Expr)); + } + + void addMEMrrOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + + Inst.addOperand(MCOperand::CreateReg(getMemBase())); + + assert(getMemOffsetReg() != 0 && "Invalid offset"); + Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg())); + } + + void addMEMriOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + + Inst.addOperand(MCOperand::CreateReg(getMemBase())); + + const MCExpr *Expr = getMemOff(); + addExpr(Inst, Expr); + } + + static SparcOperand *CreateToken(StringRef Str, SMLoc S) { + SparcOperand *Op = new SparcOperand(k_Token); + Op->Tok.Data = Str.data(); + Op->Tok.Length = Str.size(); + Op->StartLoc = S; + Op->EndLoc = S; + return Op; + } + + static SparcOperand *CreateReg(unsigned RegNum, + unsigned Kind, + SMLoc S, SMLoc E) { + SparcOperand *Op = new SparcOperand(k_Register); + Op->Reg.RegNum = RegNum; + Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + + static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { + SparcOperand *Op = new SparcOperand(k_Immediate); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + + static SparcOperand *MorphToDoubleReg(SparcOperand *Op) { + unsigned Reg = Op->getReg(); + assert(Op->Reg.Kind == rk_FloatReg); + unsigned regIdx = Reg - Sparc::F0; + if (regIdx % 2 || regIdx > 31) + return 0; + Op->Reg.RegNum = DoubleRegs[regIdx / 2]; + Op->Reg.Kind = rk_DoubleReg; + return Op; + } + + static SparcOperand *MorphToQuadReg(SparcOperand *Op) { + unsigned Reg = Op->getReg(); + unsigned regIdx = 0; + switch (Op->Reg.Kind) { + default: assert(0 && "Unexpected register kind!"); + case rk_FloatReg: + regIdx = Reg - Sparc::F0; + if (regIdx % 4 || regIdx > 31) + return 0; + Reg = QuadFPRegs[regIdx / 4]; + break; + case rk_DoubleReg: + regIdx = Reg - Sparc::D0; + if (regIdx % 2 || regIdx > 31) + return 0; + Reg = QuadFPRegs[regIdx / 2]; + break; + } + Op->Reg.RegNum = Reg; + Op->Reg.Kind = rk_QuadReg; + return Op; + } + + static SparcOperand *MorphToMEMrr(unsigned Base, SparcOperand *Op) { + unsigned offsetReg = Op->getReg(); + Op->Kind = k_MemoryReg; + Op->Mem.Base = Base; + Op->Mem.OffsetReg = offsetReg; + Op->Mem.Off = 0; + return Op; + } + + static SparcOperand *CreateMEMri(unsigned Base, + const MCExpr *Off, + SMLoc S, SMLoc E) { + SparcOperand *Op = new SparcOperand(k_MemoryImm); + Op->Mem.Base = Base; + Op->Mem.OffsetReg = 0; + Op->Mem.Off = Off; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; + } + + static SparcOperand *MorphToMEMri(unsigned Base, SparcOperand *Op) { + const MCExpr *Imm = Op->getImm(); + Op->Kind = k_MemoryImm; + Op->Mem.Base = Base; + Op->Mem.OffsetReg = 0; + Op->Mem.Off = Imm; + return Op; + } +}; + +} // end namespace + +bool SparcAsmParser:: +MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, + SmallVectorImpl<MCParsedAsmOperand*> &Operands, + MCStreamer &Out, unsigned &ErrorInfo, + bool MatchingInlineAsm) { + MCInst Inst; + SmallVector<MCInst, 8> Instructions; + unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, + MatchingInlineAsm); + switch (MatchResult) { + default: + break; + + case Match_Success: { + Inst.setLoc(IDLoc); + Out.EmitInstruction(Inst); + return false; + } + + case Match_MissingFeature: + return Error(IDLoc, + "instruction requires a CPU feature not currently enabled"); + + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U) { + if (ErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); + + ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc(); + if (ErrorLoc == SMLoc()) + ErrorLoc = IDLoc; + } + + return Error(ErrorLoc, "invalid operand for instruction"); + } + case Match_MnemonicFail: + return Error(IDLoc, "invalid instruction"); + } + return true; +} + +bool SparcAsmParser:: +ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) +{ + const AsmToken &Tok = Parser.getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); + RegNo = 0; + if (getLexer().getKind() != AsmToken::Percent) + return false; + Parser.Lex(); + unsigned regKind = SparcOperand::rk_None; + if (matchRegisterName(Tok, RegNo, regKind)) { + Parser.Lex(); + return false; + } + + return Error(StartLoc, "invalid register name"); +} + +bool SparcAsmParser:: +ParseInstruction(ParseInstructionInfo &Info, StringRef Name, + SMLoc NameLoc, + SmallVectorImpl<MCParsedAsmOperand*> &Operands) +{ + // Check if we have valid mnemonic. + if (!mnemonicIsValid(Name, 0)) { + Parser.eatToEndOfStatement(); + return Error(NameLoc, "Unknown instruction"); + } + // First operand in MCInst is instruction mnemonic. + Operands.push_back(SparcOperand::CreateToken(Name, NameLoc)); + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + // Read the first operand. + if (parseOperand(Operands, Name) != MatchOperand_Success) { + SMLoc Loc = getLexer().getLoc(); + Parser.eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + + while (getLexer().is(AsmToken::Comma)) { + Parser.Lex(); // Eat the comma. + // Parse and remember the operand. + if (parseOperand(Operands, Name) != MatchOperand_Success) { + SMLoc Loc = getLexer().getLoc(); + Parser.eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + Parser.eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + Parser.Lex(); // Consume the EndOfStatement. + return false; +} + +bool SparcAsmParser:: +ParseDirective(AsmToken DirectiveID) +{ + // Ignore all directives for now. + Parser.eatToEndOfStatement(); + return false; +} + +SparcAsmParser::OperandMatchResultTy SparcAsmParser:: +parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) +{ + + SMLoc S, E; + unsigned BaseReg = 0; + + if (ParseRegister(BaseReg, S, E)) { + return MatchOperand_NoMatch; + } + + switch (getLexer().getKind()) { + default: return MatchOperand_NoMatch; + + case AsmToken::Comma: + case AsmToken::RBrac: + case AsmToken::EndOfStatement: + Operands.push_back(SparcOperand::CreateMEMri(BaseReg, 0, S, E)); + return MatchOperand_Success; + + case AsmToken:: Plus: + Parser.Lex(); // Eat the '+' + break; + case AsmToken::Minus: + break; + } + + SparcOperand *Offset = 0; + OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset); + if (ResTy != MatchOperand_Success || !Offset) + return MatchOperand_NoMatch; + + Offset = (Offset->isImm() + ? SparcOperand::MorphToMEMri(BaseReg, Offset) + : SparcOperand::MorphToMEMrr(BaseReg, Offset)); + + Operands.push_back(Offset); + return MatchOperand_Success; +} + +SparcAsmParser::OperandMatchResultTy SparcAsmParser:: +parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, + StringRef Mnemonic) +{ + + OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); + + // If there wasn't a custom match, try the generic matcher below. Otherwise, + // there was a match, but an error occurred, in which case, just return that + // the operand parsing failed. + if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail) + return ResTy; + + if (getLexer().is(AsmToken::LBrac)) { + // Memory operand + Operands.push_back(SparcOperand::CreateToken("[", + Parser.getTok().getLoc())); + Parser.Lex(); // Eat the [ + + if (Mnemonic == "cas" || Mnemonic == "casx") { + SMLoc S = Parser.getTok().getLoc(); + if (getLexer().getKind() != AsmToken::Percent) + return MatchOperand_NoMatch; + Parser.Lex(); // eat % + + unsigned RegNo, RegKind; + if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) + return MatchOperand_NoMatch; + + Parser.Lex(); // Eat the identifier token. + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1); + Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); + ResTy = MatchOperand_Success; + } else { + ResTy = parseMEMOperand(Operands); + } + + if (ResTy != MatchOperand_Success) + return ResTy; + + if (!getLexer().is(AsmToken::RBrac)) + return MatchOperand_ParseFail; + + Operands.push_back(SparcOperand::CreateToken("]", + Parser.getTok().getLoc())); + Parser.Lex(); // Eat the ] + return MatchOperand_Success; + } + + SparcOperand *Op = 0; + ResTy = parseSparcAsmOperand(Op); + if (ResTy != MatchOperand_Success || !Op) + return MatchOperand_ParseFail; + + // Push the parsed operand into the list of operands + Operands.push_back(Op); + + return MatchOperand_Success; +} + +SparcAsmParser::OperandMatchResultTy +SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op) +{ + + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + const MCExpr *EVal; + + Op = 0; + switch (getLexer().getKind()) { + default: break; + + case AsmToken::Percent: + Parser.Lex(); // Eat the '%'. + unsigned RegNo; + unsigned RegKind; + if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) { + StringRef name = Parser.getTok().getString(); + Parser.Lex(); // Eat the identifier token. + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + switch (RegNo) { + default: + Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); + break; + case Sparc::Y: + Op = SparcOperand::CreateToken("%y", S); + break; + + case Sparc::ICC: + if (name == "xcc") + Op = SparcOperand::CreateToken("%xcc", S); + else + Op = SparcOperand::CreateToken("%icc", S); + break; + + case Sparc::FCC: + assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet"); + Op = SparcOperand::CreateToken("%fcc0", S); + break; + } + break; + } + if (matchSparcAsmModifiers(EVal, E)) { + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Op = SparcOperand::CreateImm(EVal, S, E); + } + break; + + case AsmToken::Minus: + case AsmToken::Integer: + if (!getParser().parseExpression(EVal, E)) + Op = SparcOperand::CreateImm(EVal, S, E); + break; + + case AsmToken::Identifier: { + StringRef Identifier; + if (!getParser().parseIdentifier(Identifier)) { + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier); + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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