Date: Fri, 8 Sep 2023 13:54:52 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: a35e47369f88 - main - arm64: Add TCR register masks Message-ID: <202309081354.388DsqrF005928@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=a35e47369f88e8c2e14b7371a1a5e1152680551f commit a35e47369f88e8c2e14b7371a1a5e1152680551f Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2023-09-08 13:29:19 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2023-09-08 13:31:26 +0000 arm64: Add TCR register masks These will be used by bhyve to implement page table walking. Sponsored by: Arm Ltd --- sys/arm64/include/armreg.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 3ae2f24c2a56..8251a687a5d1 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -2141,6 +2141,7 @@ #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) #define TCR_TG1_SHIFT 30 +#define TCR_TG1_MASK (3UL << TCR_TG1_SHIFT) #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) @@ -2155,8 +2156,10 @@ #define TCR_A1_SHIFT 22 #define TCR_A1 (0x1UL << TCR_A1_SHIFT) #define TCR_T1SZ_SHIFT 16 +#define TCR_T1SZ_MASK (0x3fUL << TCR_T1SZ_SHIFT) #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) #define TCR_TG0_SHIFT 14 +#define TCR_TG0_MASK (3UL << TCR_TG0_SHIFT) #define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) #define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) #define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) @@ -2170,7 +2173,7 @@ #define TCR_EPD0 (1UL << TCR_EPD0_SHIFT) /* Bit 6 is reserved */ #define TCR_T0SZ_SHIFT 0 -#define TCR_T0SZ_MASK 0x3f +#define TCR_T0SZ_MASK (0x3fUL << TCR_T0SZ_SHIFT) #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
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