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Date:      Fri, 2 Feb 1996 12:13:55 +1030 (CST)
From:      Michael Smith <msmith@atrad.adelaide.edu.au>
To:        jgreco@brasil.moneng.mei.com (Joe Greco)
Cc:        jkh@time.cdrom.com, dgy@rtd.com, freebsd-hackers@freefall.freebsd.org
Subject:   Re: Watchdog timers (was: Re: Multi-Port Async Cards)
Message-ID:  <199602020143.MAA25721@genesis.atrad.adelaide.edu.au>
In-Reply-To: <199602011630.KAA08895@brasil.moneng.mei.com> from "Joe Greco" at Feb 1, 96 10:30:11 am

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Joe Greco stands accused of saying:
> 
> I get the feeling I was barking up the right tree to begin with, but just
> didn't take it far enough.  Take a PC card.  Stick a microprocessor on it
> with two serial ports.  Connect a 16450 to the PC bus as COM1:, and hard
> wire it to one of the uP's serial ports.  You have "serial console"
> capability within FreeBSD.  Connect an output line from the uP to the PC's
> reset line.  And decode one or two I/O locations and make them available to
> the uP.

If you're going to decode the I/O's already, don't bother with the UART.
I have a rough schematic for this already, and I'll work on it when I can;
keep the ideas coming 8)

> o See log of recent events (maybe a 10K buffer that saves FreeBSD's console
>   output and writes an appropriate marker if'n'when a watchdog RESET 
>   happens, etc).

32/64K battery-backed SRAM at the moment.

> Depending on the choice of uP and its I/O capabilities, one might
> conceivably consider adding multiple point temperature monitoring and/or
> voltage monitoring as well.

8 AD inputs; conditioning for various sensors is a problem though.

> Joe Greco - Systems Administrator			      jgreco@ns.sol.net

-- 
]] Mike Smith, Software Engineer        msmith@atrad.adelaide.edu.au    [[
]] Genesis Software                     genesis@atrad.adelaide.edu.au   [[
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