Date: Wed, 27 Apr 2005 21:57:51 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/dev/uart uart_dev_z8530.c Message-ID: <200504272157.j3RLvpJ0067292@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
marcel 2005-04-27 21:57:51 UTC
FreeBSD src repository
Modified files:
sys/dev/uart uart_dev_z8530.c
Log:
Make the Z8530 more reliable as low-level console by making use of the
fact that access to RR0 does not need a prior write to the register
index because the index always reverts to 0 after the indexed register
has been accessed.
Typically when a RR or WR is to accessed, one programs the index (which
is a write to the control register), followed by a read or write to the
actual indexed register (a read pr write to the same control register).
When this non-atomic sequence is interrupted after having written the
index and low-level console I/O is done in that situation, the write to
program the index will actually write to the indexed register and nuke
state. This almost always yields a wedge.
By not programming the index register and instead just reading from RR0,
the worst case scenario is non-fatal. For if we don't actually read from
RR0 but some other register we get an invalid status, which may lead us
to conclude that the transit data register is empty when it's not or that
the receive data register contains data when it doesn't. Hence, we may
lose an output character or get a sporadic input character, but given
the situation this is a non-issue.
Full serialization is not possible due to the fact that this code needs
to work from DDB and before mutex initialization has happened.
In collaboration with: kris@, marius@
Tested by: kris@
MFC after: 1 day
X-MFC: 5.4-RELEASE candidate
Revision Changes Path
1.12 +3 -3 src/sys/dev/uart/uart_dev_z8530.c
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200504272157.j3RLvpJ0067292>