Date: Thu, 24 Oct 2024 02:41:46 GMT From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 6308db659f2a - main - x86 specialreg: add bit masks definitions for EFER features Message-ID: <202410240241.49O2fkXb078730@gitrepo.freebsd.org>
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The branch main has been updated by kib: URL: https://cgit.FreeBSD.org/src/commit/?id=6308db659f2ad45b30bbf1d9c47abdc97d14ebb0 commit 6308db659f2ad45b30bbf1d9c47abdc97d14ebb0 Author: Konstantin Belousov <kib@FreeBSD.org> AuthorDate: 2024-10-23 23:21:11 +0000 Commit: Konstantin Belousov <kib@FreeBSD.org> CommitDate: 2024-10-24 02:41:10 +0000 x86 specialreg: add bit masks definitions for EFER features listed in AMD64 APM vol.2 rev. 3.42. Sponsored by: The FreeBSD Foundation MFC after: 1 week --- sys/x86/include/specialreg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 197ae4bba7a1..ab172ec54ff6 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -105,6 +105,9 @@ #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ #define EFER_TCE 0x000008000 /* Translation Cache Extension */ #define EFER_MCOMMIT 0x000020000 /* Enable MCOMMIT (AMD) */ +#define EFER_INTWB 0x000040000 /* Interruptible WBINVD */ +#define EFER_UAIE 0x000100000 /* Upper Address Ignore */ +#define EFER_AIBRSE 0x000200000 /* Automatic IBRS */ /* * Intel Extended Features registers
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