Date: Wed, 23 Jan 2008 23:24:03 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 133961 for review Message-ID: <200801232324.m0NNO3ta027166@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=133961 Change 133961 by imp@imp_paco-paco on 2008/01/23 23:23:16 Convert exception.S to new world order. Note in passing the need for some of this stuff to be common. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#6 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#6 (text+ko) ==== @@ -54,6 +54,7 @@ * assembly language support routines. */ +#include "opt_cputype.h" #include "opt_ddb.h" #include <machine/asm.h> #include <machine/cpu.h> @@ -62,8 +63,35 @@ #include "assym.s" - .set noreorder # Noreorder is default style! -#ifndef _MIPS_ARCH_MIPS64 +#if defined(ISA_MIPS32) +#undef WITH_64BIT_CP0 +#elif defined(ISA_MIPS64) +#define WITH_64BIT_CP0 +#elif defined(ISA_MIPS3) +#define WITH_64BIT_CP0 +#else +#error "Please write the code for this ISA" +#endif + +#ifdef WITH_64BIT_CP0 +#define _SLL dsll +#define _SRL dsrl +#define _MFC0 dmfc0 +#define _MTC0 dmtc0 +#define WIRED_SHIFT 34 +#else +#define _SLL sll +#define _SRL srl +#define _MFC0 mfc0 +#define _MTC0 mtc0 +#define WIRED_SHIFT 2 +#endif + .set noreorder # Noreorder is default style! +#if defined(ISA_MIPS32) + .set mips32 +#elif defined(ISA_MIPS64) + .set mips64 +#elif defined(ISA_MIPS3) .set mips3 #endif @@ -136,12 +164,12 @@ addu k1, k1, k0 #0d: k1=pte address lw k0, 0(k1) #0e: k0=lo0 pte lw k1, 4(k1) #0f: k1=lo1 pte - dsll k0, k0, 34 #10: chop top 34 bits (part 1a) - dsrl k0, k0, 34 #11: chop top 34 bits (part 1b) - dmtc0 k0, COP_0_TLB_LO0 #12: lo0 is loaded - dsll k1, k1, 34 #13: chop top 34 bits (part 2a) - dsrl k1, k1, 34 #14: chop top 34 bits (part 2b) - dmtc0 k1, COP_0_TLB_LO1 #15: lo1 is loaded + _SLL k0, k0, WIRED_SHIFT #10: keep bottom 30 bits + _SRL k0, k0, WIRED_SHIFT #11: keep bottom 30 bits + _MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded + _SLL k1, k1, WIRED_SHIFT #13: keep bottom 30 bits + _SRL k1, k1, WIRED_SHIFT #14: keep bottom 30 bits + _MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded HAZARD_DELAY tlbwr #1a: write to tlb HAZARD_DELAY @@ -292,7 +320,7 @@ mtc0 a0, COP_0_STATUS_REG ;\ mtlo t0 ;\ mthi t1 ;\ - dmtc0 v0, COP_0_EXC_PC ;\ + _MTC0 v0, COP_0_EXC_PC ;\ RESTORE_REG(AT, AST, sp) ;\ RESTORE_REG(v0, V0, sp) ;\ RESTORE_REG(v1, V1, sp) ;\ @@ -378,6 +406,7 @@ GET_CPU_PCPU(k1) lw k1, PC_CURPCB(k1) SAVE_U_PCB_REG(AT, AST, k1) + .set at SAVE_U_PCB_REG(v0, V0, k1) SAVE_U_PCB_REG(v1, V1, k1) SAVE_U_PCB_REG(a0, A0, k1) @@ -452,9 +481,10 @@ mtlo t0 mthi t1 RESTORE_U_PCB_REG(a0, PC, a1) + .set noat RESTORE_U_PCB_REG(AT, AST, a1) RESTORE_U_PCB_REG(v0, V0, a1) - dmtc0 a0, COP_0_EXC_PC # set return address + _MTC0 a0, COP_0_EXC_PC # set return address /* * The use of k1 for storing the PCB pointer must be done only @@ -694,7 +724,7 @@ RESTORE_U_PCB_REG(t2, PC, a1) mtlo t0 mthi t1 - dmtc0 t2, COP_0_EXC_PC # set return address + _MTC0 t2, COP_0_EXC_PC # set return address /* * The use of k1 to store the PCB pointer must be done only @@ -820,16 +850,16 @@ bne k0, zero, sys_stk_chk lw k0, 0(k1) # get PTE entry - dsll k0, k0, 34 # get rid of "wired" bit - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO0 # load PTE entry + _SLL k0, k0, WIRED_SHIFT # get rid of "wired" bit + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO0 # load PTE entry and k0, k0, PG_V # check for valid entry nop # required for QED5230 beq k0, zero, _C_LABEL(MipsKernGenException) # PTE invalid lw k0, 4(k1) # get odd PTE entry - dsll k0, k0, 34 - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO1 # load PTE entry + _SLL k0, k0, WIRED_SHIFT + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO1 # load PTE entry HAZARD_DELAY tlbwi # write TLB HAZARD_DELAY @@ -844,16 +874,16 @@ bne k0, zero, sys_stk_chk lw k0, 0(k1) # get PTE entry - dsll k0, k0, 34 # get rid of wired bit - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO1 # save PTE entry + _SLL k0, k0, WIRED_SHIFT # get rid of wired bit + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO1 # save PTE entry and k0, k0, PG_V # check for valid entry nop # required for QED5230 beq k0, zero, _C_LABEL(MipsKernGenException) # PTE invalid lw k0, -4(k1) # get even PTE entry - dsll k0, k0, 34 - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO0 # save PTE entry + _SLL k0, k0, WIRED_SHIFT + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO0 # save PTE entry HAZARD_DELAY tlbwi # update TLB HAZARD_DELAY @@ -904,16 +934,16 @@ bne k0, zero, _C_LABEL(MipsUserGenException) lw k0, 0(k1) # get PTE entry - dsll k0, k0, 34 # get rid of "wired" bit - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO0 # load PTE entry + _SLL k0, k0, WIRED_SHIFT # get rid of "wired" bit + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO0 # load PTE entry and k0, k0, PG_V # check for valid entry nop # required for QED5230 beq k0, zero, _C_LABEL(MipsUserGenException) # PTE invalid lw k0, 4(k1) # get odd PTE entry - dsll k0, k0, 34 - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO1 # load PTE entry + _SLL k0, k0, WIRED_SHIFT + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO1 # load PTE entry HAZARD_DELAY tlbwi # write TLB HAZARD_DELAY @@ -928,16 +958,16 @@ bne k0, zero, _C_LABEL(MipsUserGenException) lw k0, 0(k1) # get PTE entry - dsll k0, k0, 34 # get rid of wired bit - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO1 # save PTE entry + _SLL k0, k0, WIRED_SHIFT # get rid of wired bit + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO1 # save PTE entry and k0, k0, PG_V # check for valid entry nop # required for QED5230 beq k0, zero, _C_LABEL(MipsUserGenException) # PTE invalid lw k0, -4(k1) # get even PTE entry - dsll k0, k0, 34 - dsrl k0, k0, 34 - dmtc0 k0, COP_0_TLB_LO0 # save PTE entry + _SLL k0, k0, WIRED_SHIFT + _SRL k0, k0, WIRED_SHIFT + _MTC0 k0, COP_0_TLB_LO0 # save PTE entry HAZARD_DELAY tlbwi # update TLB HAZARD_DELAY @@ -982,12 +1012,12 @@ addu k1, k1, k0 # k1=pte address lw k0, 0(k1) # k0=lo0 pte lw k1, 4(k1) # k1=lo1 pte - dsll k0, 34 # chop bits [31..30] - dsrl k0, 34 # chop bits [31..30] - dmtc0 k0, COP_0_TLB_LO0 # lo0 is loaded - dsll k1, 34 # chop bits [31..30] - dsrl k1, 34 # chop bits [31..30] - dmtc0 k1, COP_0_TLB_LO1 # lo1 is loaded + _SLL k0, WIRED_SHIFT # chop bits [31..30] + _SRL k0, WIRED_SHIFT # chop bits [31..30] + _MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded + _SLL k1, WIRED_SHIFT # chop bits [31..30] + _SRL k1, WIRED_SHIFT # chop bits [31..30] + _MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded HAZARD_DELAY tlbwr # write to tlb @@ -1009,7 +1039,7 @@ la a0, 1f mfc0 a2, COP_0_STATUS_REG mfc0 a3, COP_0_CAUSE_REG - dmfc0 a1, COP_0_EXC_PC + _MFC0 a1, COP_0_EXC_PC sw a2, 16(sp) sw a3, 20(sp) move a2, ra @@ -1235,10 +1265,10 @@ .mask 0x80000000, -4 la k0, _C_LABEL(panic) # return to panic la a0, 9f # panicstr - dmfc0 a1, COP_0_ERROR_PC + _MFC0 a1, COP_0_ERROR_PC mfc0 a2, COP_0_CACHE_ERR # 3rd arg cache error - dmtc0 k0, COP_0_ERROR_PC # set return address + _MTC0 k0, COP_0_ERROR_PC # set return address mfc0 k0, COP_0_STATUS_REG # restore status li k1, SR_DIAG_DE # ignore further errors @@ -1250,5 +1280,4 @@ MSG("cache error @ EPC 0x%x CachErr 0x%x"); .set at - .set mips2 END(MipsCacheException)
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