Date: Sat, 31 Dec 2016 01:54:48 +0000 (UTC) From: Luiz Otavio O Souza <loos@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r310882 - stable/11/sys/arm/ti/cpsw Message-ID: <201612310154.uBV1smrt016696@repo.freebsd.org>
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Author: loos Date: Sat Dec 31 01:54:48 2016 New Revision: 310882 URL: https://svnweb.freebsd.org/changeset/base/310882 Log: MFC r309345: The RX_FREEBUFFER registers are a write to increment field. Writing the full queue size to it every time was makeing it overflow with a lot of bogus values. This fixes the interrupt storms on irq 40. MFC r309347: MDIO_PHYACCESS_ACK is only valid for read access, remove it from miibus_writereg. Reduce the DELAY() between reads while waiting for MII access. Spotted by: yongari Sponsored by: Rubicon Communications, LLC (Netgate) Modified: stable/11/sys/arm/ti/cpsw/if_cpsw.c stable/11/sys/arm/ti/cpsw/if_cpswvar.h Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/arm/ti/cpsw/if_cpsw.c ============================================================================== --- stable/11/sys/arm/ti/cpsw/if_cpsw.c Sat Dec 31 01:51:41 2016 (r310881) +++ stable/11/sys/arm/ti/cpsw/if_cpsw.c Sat Dec 31 01:54:48 2016 (r310882) @@ -1513,9 +1513,6 @@ cpswp_miibus_writereg(device_t dev, int return (0); } - if ((cpsw_read_4(sc->swsc, sc->phyaccess) & MDIO_PHYACCESS_ACK) == 0) - device_printf(dev, "Failed to write to PHY.\n"); - return (0); } @@ -1761,7 +1758,7 @@ cpsw_rx_enqueue(struct cpsw_softc *sc) sc->rx.queue_adds += added; sc->rx.avail_queue_len -= added; sc->rx.active_queue_len += added; - cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); + cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) { sc->rx.max_active_queue_len = sc->rx.active_queue_len; } Modified: stable/11/sys/arm/ti/cpsw/if_cpswvar.h ============================================================================== --- stable/11/sys/arm/ti/cpsw/if_cpswvar.h Sat Dec 31 01:51:41 2016 (r310881) +++ stable/11/sys/arm/ti/cpsw/if_cpswvar.h Sat Dec 31 01:54:48 2016 (r310882) @@ -33,8 +33,8 @@ #define CPSW_INTR_COUNT 4 /* MII BUS */ -#define CPSW_MIIBUS_RETRIES 5 -#define CPSW_MIIBUS_DELAY 1000 +#define CPSW_MIIBUS_RETRIES 20 +#define CPSW_MIIBUS_DELAY 100 #define CPSW_MAX_ALE_ENTRIES 1024
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