Date: Wed, 23 Jan 2008 23:32:13 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 133962 for review Message-ID: <200801232332.m0NNWDsb027454@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=133962 Change 133962 by imp@imp_paco-paco on 2008/01/23 23:31:47 Convert this over. Now we're getting to this point in the boot: Device configuration finished. cpu_initclocks(): stathz = 0xd, profhz = 0x42 Timecounter "mips" frequency 0 Hz quality -2143494216 mips_timer_init: starting the real time clock. mips_timer_init: cpu_counter_interval = 0x7a120 Timecounters tick every 10.000 msec St[ warning: LOW reference: vaddr=0x00000000, exception TLBL, pc=0x00000000 <(no symbol)> ] not sure why we jump to location 0 in the kernel, but it is likely something to do with mips_cpu_switch. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#7 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#7 (text+ko) ==== @@ -55,7 +55,7 @@ * assembly language support routines. */ - +#include "opt_cputype.h" #include <sys/syscall.h> #include <machine/asm.h> #include <machine/cpu.h> @@ -65,7 +65,39 @@ #include "assym.s" -#ifndef MIPS_ISAIII +#if defined(ISA_MIPS32) +#undef WITH_64BIT_CP0 +#elif defined(ISA_MIPS64) +#define WITH_64BIT_CP0 +#elif defined(ISA_MIPS3) +#define WITH_64BIT_CP0 +#else +#error "Please write the code for this ISA" +#endif + +#ifdef WITH_64BIT_CP0 +#define _SLL dsll +#define _SRL dsrl +#define _MFC0 dmfc0 +#define _MTC0 dmtc0 +#define WIRED_SHIFT 34 +#else +#define _SLL sll +#define _SRL srl +#define _MFC0 mfc0 +#define _MTC0 mtc0 +#define WIRED_SHIFT 2 +#endif + .set noreorder # Noreorder is default style! +#if defined(ISA_MIPS32) + .set mips32 +#elif defined(ISA_MIPS64) + .set mips64 +#elif defined(ISA_MIPS3) + .set mips3 +#endif + +#if defined(ISA_MIPS32) #define STORE sw /* 32 bit mode regsave instruction */ #define LOAD lw /* 32 bit mode regload instruction */ #define RSIZE 4 /* 32 bit mode register size */ @@ -86,7 +118,7 @@ * Some MIPS CPU may need delays using nops between executing CP0 Instructions */ -#ifdef MIPS_CPU_NEEDS_DELAY +#if 1 #define HAZARD_DELAY nop ; nop ; nop ; nop #else #define HAZARD_DELAY @@ -116,11 +148,6 @@ #define RESTORE_U_PCB_CONTEXT(reg, offs, base) \ LOAD reg, U_PCB_CONTEXT + (RSIZE * offs) (base) - .set noreorder # Noreorder is default style! -#ifndef _MIPS_ARCH_MIPS64 - .set mips3 -#endif - #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; /* @@ -155,7 +182,7 @@ RESTORE_U_PCB_REG(a0, PC, a1) RESTORE_U_PCB_REG(AT, AST, a1) RESTORE_U_PCB_REG(v0, V0, a1) - dmtc0 a0, COP_0_EXC_PC # set return address + _MTC0 a0, COP_0_EXC_PC # set return address /* * The use of k1 for storing the PCB pointer must be done only @@ -608,4 +635,3 @@ szsigcode: .long esigcode-sigcode .text - .set mips2
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