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Date:      Wed, 11 Mar 2009 17:14:17 +0000 (UTC)
From:      Sam Leffler <sam@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r189701 - head/tools/tools/ath/athregs
Message-ID:  <200903111714.n2BHEHxp001708@svn.freebsd.org>

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Author: sam
Date: Wed Mar 11 17:14:17 2009
New Revision: 189701
URL: http://svn.freebsd.org/changeset/base/189701

Log:
  add %b format strings for use by athdecode

Modified:
  head/tools/tools/ath/athregs/dumpregs.h
  head/tools/tools/ath/athregs/dumpregs_5210.c
  head/tools/tools/ath/athregs/dumpregs_5211.c
  head/tools/tools/ath/athregs/dumpregs_5212.c
  head/tools/tools/ath/athregs/dumpregs_5416.c

Modified: head/tools/tools/ath/athregs/dumpregs.h
==============================================================================
--- head/tools/tools/ath/athregs/dumpregs.h	Wed Mar 11 16:32:00 2009	(r189700)
+++ head/tools/tools/ath/athregs/dumpregs.h	Wed Mar 11 17:14:17 2009	(r189701)
@@ -36,6 +36,7 @@
 struct dumpreg {
 	uint32_t	addr;
 	const char	*name;
+	const char	*bits;
 	int		type;
 	u_int		srevMin, srevMax;
 	u_int		phyMin, phyMax;
@@ -61,6 +62,30 @@ enum {
 	DUMP_ALL	= 0xffff
 };
 
+#define	_DEFREG(_addr, _name, _type) \
+    { .addr = _addr, .name = _name, .type = _type }
+#define	_DEFREGx(_addr, _name, _type, _srevmin, _srevmax) \
+    { .addr = _addr, .name = _name, .type = _type, \
+     .srevMin = _srevmin, .srevMax = _srevmax }
+#define	_DEFREGfmt(_addr, _name, _type, _fmt) \
+    { .addr = _addr, .name = _name, .type = _type, .bits = _fmt }
+#define	DEFVOID(_addr, _name)	_DEFREG(_addr, _name, 0)
+#define	DEFVOIDx(_addr, _name, _smin, _smax) \
+	__DEFREGx(_addr, _name, _smin, _smax, 0)
+#define	DEFVOIDfmt(_addr, _name, _fmt) \
+	_DEFREGfmt(_addr, _name, 0, _fmt)
+#define	DEFBASIC(_addr, _name)	_DEFREG(_addr, _name, DUMP_BASIC)
+#define	DEFBASICfmt(_addr, _name, _fmt) \
+	_DEFREGfmt(_addr, _name, DUMP_BASIC, _fmt)
+#define	DEFBASICx(_addr, _name, _smin, _smax) \
+	_DEFREGx(_addr, _name, DUMP_BASIC, _smin, _smax)
+#define	DEFBB(_addr, _name)	_DEFREG(_addr, _name, DUMP_BASEBAND)
+#define	DEFINT(_addr, _name)	_DEFREG(_addr, _name, DUMP_INTERRUPT)
+#define	DEFINTfmt(_addr, _name, _fmt) \
+	_DEFREGfmt(_addr, _name, DUMP_INTERRUPT, _fmt)
+#define	DEFQCU(_addr, _name)	_DEFREG(_addr, _name, DUMP_QCU)
+#define	DEFDCU(_addr, _name)	_DEFREG(_addr, _name, DUMP_DCU)
+
 void	register_regs(struct dumpreg *_regs, u_int _nregs,
 	    int def_srev_min, int def_srev_max,
 	    int def_phy_min, int def_phy_max);

Modified: head/tools/tools/ath/athregs/dumpregs_5210.c
==============================================================================
--- head/tools/tools/ath/athregs/dumpregs_5210.c	Wed Mar 11 16:32:00 2009	(r189700)
+++ head/tools/tools/ath/athregs/dumpregs_5210.c	Wed Mar 11 17:14:17 2009	(r189701)
@@ -33,83 +33,85 @@
 #include "ah.h"
 #include "ah_internal.h"
 #include "ar5210/ar5210reg.h"
+#include "ar5210/ar5210phy.h"
 
 #include "dumpregs.h"
 
 #define	N(a)	(sizeof(a) / sizeof(a[0]))
 
 static struct dumpreg ar5210regs[] = {
-    { AR_TXDP0,		"TXDP0",	DUMP_BASIC },
-    { AR_TXDP1,		"TXDP1",	DUMP_BASIC },
-    { AR_CR,		"CR",		DUMP_BASIC },
-    { AR_RXDP,		"RXDP",		DUMP_BASIC },
-    { AR_CFG,		"CFG",		DUMP_BASIC },
-#if 0	/* read clears pending interrupts */
-    { AR_ISR,		"ISR",		DUMP_INTERRUPT },
-#endif
-    { AR_IMR,		"IMR",		DUMP_BASIC },
-    { AR_IER,		"IER",		DUMP_BASIC },
-    { AR_BCR,		"BCR",		DUMP_BASIC },
-    { AR_BSR,		"BSR",		DUMP_BASIC },
-    { AR_TXCFG,		"TXCFG",	DUMP_BASIC },
-    { AR_RXCFG,		"RXCFG",	DUMP_BASIC },
-    { AR_MIBC,		"MIBC",		DUMP_BASIC },
-    { AR_TOPS,		"TOPS",		DUMP_BASIC },
-    { AR_RXNOFRM,	"RXNOFR",	DUMP_BASIC },
-    { AR_TXNOFRM,	"TXNOFR",	DUMP_BASIC },
-    { AR_RPGTO,		"RPGTO",	DUMP_BASIC },
-    { AR_RFCNT,		"RFCNT",	DUMP_BASIC },
-    { AR_MISC,		"MISC",		DUMP_BASIC },
-    { AR_RC,		"RC",		DUMP_BASIC },
-    { AR_SCR,		"SCR",		DUMP_BASIC },
-    { AR_INTPEND,	"INTPEND",	DUMP_BASIC },
-    { AR_SFR,		"SFR",		DUMP_BASIC },
-    { AR_PCICFG,	"PCICFG",	DUMP_BASIC },
-    { AR_GPIOCR,	"GPIOCR",	DUMP_BASIC },
-#if 0
-    { AR_GPIODO,	"GPIODO",	DUMP_BASIC },
-    { AR_GPIODI,	"GPIODI",	DUMP_BASIC },
-#endif
-    { AR_SREV,		"SREV",		DUMP_BASIC },
-    { AR_STA_ID0,	"STA_ID0",	DUMP_BASIC },
-    { AR_STA_ID1,	"STA_ID1",	DUMP_BASIC },
-    { AR_BSS_ID0,	"BSS_ID0",	DUMP_BASIC },
-    { AR_BSS_ID1,	"BSS_ID1",	DUMP_BASIC },
-    { AR_SLOT_TIME,	"SLOTTIME",	DUMP_BASIC },
-    { AR_TIME_OUT,	"TIME_OUT",	DUMP_BASIC },
-    { AR_RSSI_THR,	"RSSI_THR",	DUMP_BASIC },
-    { AR_RETRY_LMT,	"RETRY_LM",	DUMP_BASIC },
-    { AR_USEC,		"USEC",		DUMP_BASIC },
-    { AR_BEACON,	"BEACON",	DUMP_BASIC },
-    { AR_CFP_PERIOD,	"CFP_PER",	DUMP_BASIC },
-    { AR_TIMER0,	"TIMER0",	DUMP_BASIC },
-    { AR_TIMER1,	"TIMER1",	DUMP_BASIC },
-    { AR_TIMER2,	"TIMER2",	DUMP_BASIC },
-    { AR_TIMER3,	"TIMER3",	DUMP_BASIC },
-    { AR_IFS0,		"IFS0",		DUMP_BASIC },
-    { AR_IFS1,		"IFS1"	,	DUMP_BASIC },
-    { AR_CFP_DUR,	"CFP_DUR",	DUMP_BASIC },
-    { AR_RX_FILTER,	"RXFILTER",	DUMP_BASIC },
-    { AR_MCAST_FIL0,	"MCAST_0",	DUMP_BASIC },
-    { AR_MCAST_FIL1,	"MCAST_1",	DUMP_BASIC },
-    { AR_TX_MASK0,	"TX_MASK0",	DUMP_BASIC },
-    { AR_TX_MASK1,	"TX_MASK1",	DUMP_BASIC },
-#if 0
-    { AR_CLR_TMASK,	"CLR_TMASK",	DUMP_BASIC },
-#endif
-    { AR_TRIG_LEV,	"TRIG_LEV",	DUMP_BASIC },
-    { AR_DIAG_SW,	"DIAG_SW",	DUMP_BASIC },
-    { AR_TSF_L32,	"TSF_L32",	DUMP_BASIC },
-    { AR_TSF_U32,	"TSF_U32",	DUMP_BASIC },
-    { AR_LAST_TSTP,	"LAST_TST",	DUMP_BASIC },
-    { AR_RETRY_CNT,	"RETRYCNT",	DUMP_BASIC },
-    { AR_BACKOFF,	"BACKOFF",	DUMP_BASIC },
-    { AR_NAV,		"NAV",		DUMP_BASIC },
-    { AR_RTS_OK,	"RTS_OK",	DUMP_BASIC },
-    { AR_RTS_FAIL,	"RTS_FAIL",	DUMP_BASIC },
-    { AR_ACK_FAIL,	"ACK_FAIL",	DUMP_BASIC },
-    { AR_FCS_FAIL,	"FCS_FAIL",	DUMP_BASIC },
-    { AR_BEACON_CNT,	"BEAC_CNT",	DUMP_BASIC },
+    DEFBASIC(AR_TXDP0,		"TXDP0"),
+    DEFBASIC(AR_TXDP1,		"TXDP1"),
+    DEFBASICfmt(AR_CR,		"CR",		AR_CR_BITS),
+    DEFBASIC(AR_RXDP,		"RXDP"),
+    DEFBASICfmt(AR_CFG,		"CFG",		AR_CFG_BITS),
+    /* NB: read clears pending interrupts */
+    DEFVOIDfmt(AR_ISR,		"ISR",		AR_ISR_BITS),
+    DEFBASICfmt(AR_IMR,		"IMR",		AR_IMR_BITS),
+    DEFBASICfmt(AR_IER,		"IER",		AR_IER_BITS),
+    DEFBASICfmt(AR_BCR,		"BCR",		AR_BCR_BITS),
+    DEFBASICfmt(AR_BSR,		"BSR",		AR_BSR_BITS),
+    DEFBASICfmt(AR_TXCFG,	"TXCFG",	AR_TXCFG_BITS),
+    DEFBASIC(AR_RXCFG,		"RXCFG"),
+    DEFBASIC(AR_MIBC,		"MIBC"),
+    DEFBASIC(AR_TOPS,		"TOPS"),
+    DEFBASIC(AR_RXNOFRM,	"RXNOFR"),
+    DEFBASIC(AR_TXNOFRM,	"TXNOFR"),
+    DEFBASIC(AR_RPGTO,		"RPGTO"),
+    DEFBASIC(AR_RFCNT,		"RFCNT"),
+    DEFBASIC(AR_MISC,		"MISC"),
+    DEFBASICfmt(AR_RC,		"RC",		AR_RC_BITS),
+    DEFBASICfmt(AR_SCR,		"SCR",		AR_SCR_BITS),
+    DEFBASICfmt(AR_INTPEND,	"INTPEND",	AR_INTPEND_BITS),
+    DEFBASIC(AR_SFR,		"SFR"),
+    DEFBASICfmt(AR_PCICFG,	"PCICFG",	AR_PCICFG_BITS),
+    DEFBASIC(AR_GPIOCR,		"GPIOCR"),
+    DEFVOID(AR_GPIODO,		"GPIODO"),
+    DEFVOID(AR_GPIODI,		"GPIODI"),
+    DEFBASIC(AR_SREV,		"SREV"),
+    DEFBASIC(AR_STA_ID0,	"STA_ID0"),
+    DEFBASICfmt(AR_STA_ID1,	"STA_ID1",	AR_STA_ID1_BITS),
+    DEFBASIC(AR_BSS_ID0,	"BSS_ID0"),
+    DEFBASIC(AR_BSS_ID1,	"BSS_ID1"),
+    DEFBASIC(AR_SLOT_TIME,	"SLOTTIME"),
+    DEFBASIC(AR_TIME_OUT,	"TIME_OUT"),
+    DEFBASIC(AR_RSSI_THR,	"RSSI_THR"),
+    DEFBASIC(AR_RETRY_LMT,	"RETRY_LM"),
+    DEFBASIC(AR_USEC,		"USEC"),
+    DEFBASICfmt(AR_BEACON,		"BEACON",	AR_BEACON_BITS),
+    DEFBASIC(AR_CFP_PERIOD,	"CFP_PER"),
+    DEFBASIC(AR_TIMER0,		"TIMER0"),
+    DEFBASIC(AR_TIMER1,		"TIMER1"),
+    DEFBASIC(AR_TIMER2,		"TIMER2"),
+    DEFBASIC(AR_TIMER3,		"TIMER3"),
+    DEFBASIC(AR_IFS0,		"IFS0"),
+    DEFBASIC(AR_IFS1,		"IFS1"	),
+    DEFBASIC(AR_CFP_DUR,	"CFP_DUR"),
+    DEFBASICfmt(AR_RX_FILTER,	"RXFILTER",	AR_BEACON_BITS),
+    DEFBASIC(AR_MCAST_FIL0,	"MCAST_0"),
+    DEFBASIC(AR_MCAST_FIL1,	"MCAST_1"),
+    DEFBASIC(AR_TX_MASK0,	"TX_MASK0"),
+    DEFBASIC(AR_TX_MASK1,	"TX_MASK1"),
+    DEFVOID(AR_CLR_TMASK,	"CLR_TMASK"),
+    DEFBASIC(AR_TRIG_LEV,	"TRIG_LEV"),
+    DEFBASICfmt(AR_DIAG_SW,	"DIAG_SW",	AR_DIAG_SW_BITS),
+    DEFBASIC(AR_TSF_L32,	"TSF_L32"),
+    DEFBASIC(AR_TSF_U32,	"TSF_U32"),
+    DEFBASIC(AR_LAST_TSTP,	"LAST_TST"),
+    DEFBASIC(AR_RETRY_CNT,	"RETRYCNT"),
+    DEFBASIC(AR_BACKOFF,	"BACKOFF"),
+    DEFBASIC(AR_NAV,		"NAV"),
+    DEFBASIC(AR_RTS_OK,		"RTS_OK"),
+    DEFBASIC(AR_RTS_FAIL,	"RTS_FAIL"),
+    DEFBASIC(AR_ACK_FAIL,	"ACK_FAIL"),
+    DEFBASIC(AR_FCS_FAIL,	"FCS_FAIL"),
+    DEFBASIC(AR_BEACON_CNT,	"BEAC_CNT"),
+
+    DEFVOIDfmt(AR_PHY_FRCTL,	"PHY_FRCTL",	AR_PHY_FRCTL_BITS),
+    DEFVOIDfmt(AR_PHY_AGC,	"PHY_AGC",	AR_PHY_AGC_BITS),
+    DEFVOID(AR_PHY_CHIPID,	"PHY_CHIPID"),
+    DEFVOIDfmt(AR_PHY_ACTIVE,	"PHY_ACTIVE",	AR_PHY_ACTIVE_BITS),
+    DEFVOIDfmt(AR_PHY_AGCCTL,	"PHY_AGCCTL",	AR_PHY_AGCCTL_BITS),
 };
 
 static __constructor void

Modified: head/tools/tools/ath/athregs/dumpregs_5211.c
==============================================================================
--- head/tools/tools/ath/athregs/dumpregs_5211.c	Wed Mar 11 16:32:00 2009	(r189700)
+++ head/tools/tools/ath/athregs/dumpregs_5211.c	Wed Mar 11 17:14:17 2009	(r189701)
@@ -33,239 +33,251 @@
 #include "ah.h"
 #include "ah_internal.h"
 #include "ar5211/ar5211reg.h"
+#include "ar5211/ar5211phy.h"
 
 #include "dumpregs.h"
 
 #define	N(a)	(sizeof(a) / sizeof(a[0]))
 
 static struct dumpreg ar5211regs[] = {
-    { AR_CR,		"CR",		DUMP_BASIC },
-    { AR_RXDP,		"RXDP",		DUMP_BASIC },
-    { AR_CFG,		"CFG",		DUMP_BASIC },
-    { AR_IER,		"IER",		DUMP_BASIC },
-    { AR_RTSD0,		"RTSD0",	DUMP_BASIC },
-    { AR_RTSD1,		"RTSD1",	DUMP_BASIC },
-    { AR_TXCFG,		"TXCFG",	DUMP_BASIC },
-    { AR_RXCFG,		"RXCFG",	DUMP_BASIC },
-    { AR5211_JUMBO_LAST,"JLAST",	DUMP_BASIC },
-    { AR_MIBC,		"MIBC",		DUMP_BASIC },
-    { AR_TOPS,		"TOPS",		DUMP_BASIC },
-    { AR_RXNPTO,	"RXNPTO",	DUMP_BASIC },
-    { AR_TXNPTO,	"TXNPTO",	DUMP_BASIC },
-    { AR_RFGTO,		"RFGTO",	DUMP_BASIC },
-    { AR_RFCNT,		"RFCNT",	DUMP_BASIC },
-    { AR_MACMISC,	"MISC",		DUMP_BASIC },
-
-    { AR_ISR,		"ISR",		DUMP_INTERRUPT },
-    { AR_ISR_S0,	"ISR_S0",	DUMP_INTERRUPT },
-    { AR_ISR_S1,	"ISR_S1",	DUMP_INTERRUPT },
-    { AR_ISR_S2,	"ISR_S2",	DUMP_INTERRUPT },
-    { AR_ISR_S3,	"ISR_S3",	DUMP_INTERRUPT },
-    { AR_ISR_S4,	"ISR_S4",	DUMP_INTERRUPT },
-    { AR_IMR,		"IMR",		DUMP_INTERRUPT },
-    { AR_IMR_S0,	"IMR_S0",	DUMP_INTERRUPT },
-    { AR_IMR_S1,	"IMR_S1",	DUMP_INTERRUPT },
-    { AR_IMR_S2,	"IMR_S2",	DUMP_INTERRUPT },
-    { AR_IMR_S3,	"IMR_S3",	DUMP_INTERRUPT },
-    { AR_IMR_S4,	"IMR_S4",	DUMP_INTERRUPT },
-#if 0
+    DEFBASICfmt(AR_CR,		"CR",		AR_CR_BITS),
+    DEFBASIC(AR_RXDP,		"RXDP"),
+    DEFBASICfmt(AR_CFG,		"CFG",		AR_CFG_BITS),
+    DEFBASICfmt(AR_IER,		"IER",		AR_IER_BITS),
+    DEFBASIC(AR_RTSD0,		"RTSD0"),
+    DEFBASIC(AR_RTSD1,		"RTSD1"),
+    DEFBASICfmt(AR_TXCFG,	"TXCFG",	AR_TXCFG_BITS),
+    DEFBASIC(AR_RXCFG,		"RXCFG"),
+    DEFBASIC(AR5211_JUMBO_LAST,	"JLAST"),
+    DEFBASIC(AR_MIBC,		"MIBC"),
+    DEFBASIC(AR_TOPS,		"TOPS"),
+    DEFBASIC(AR_RXNPTO,		"RXNPTO"),
+    DEFBASIC(AR_TXNPTO,		"TXNPTO"),
+    DEFBASIC(AR_RFGTO,		"RFGTO"),
+    DEFBASIC(AR_RFCNT,		"RFCNT"),
+    DEFBASIC(AR_MACMISC,	"MISC"),
+    DEFVOID(AR5311_QDCLKGATE,	"AR5311_QDCLKGATE"),
+
+    DEFINT(AR_ISR,		"ISR"),
+    DEFINT(AR_ISR_S0,		"ISR_S0"),
+    DEFINT(AR_ISR_S1,		"ISR_S1"),
+    DEFINT(AR_ISR_S2,		"ISR_S2"),
+    DEFINT(AR_ISR_S3,		"ISR_S3"),
+    DEFINT(AR_ISR_S4,		"ISR_S4"),
+    DEFINT(AR_IMR,		"IMR"),
+    DEFINT(AR_IMR_S0,		"IMR_S0"),
+    DEFINT(AR_IMR_S1,		"IMR_S1"),
+    DEFINT(AR_IMR_S2,		"IMR_S2"),
+    DEFINT(AR_IMR_S3,		"IMR_S3"),
+    DEFINT(AR_IMR_S4,		"IMR_S4"),
     /* NB: don't read the RAC so we don't affect operation */
-    { AR_ISR_RAC,	"ISR_RAC",	DUMP_INTERRUPT },
-#endif
-    { AR_ISR_S0_S,	"ISR_S0_S",	DUMP_INTERRUPT },
-    { AR_ISR_S1_S,	"ISR_S1_S",	DUMP_INTERRUPT },
-    { AR_ISR_S2_S,	"ISR_S2_S",	DUMP_INTERRUPT },
-    { AR_ISR_S3_S,	"ISR_S3_S",	DUMP_INTERRUPT },
-    { AR_ISR_S4_S,	"ISR_S4_S",	DUMP_INTERRUPT },
-
-    { AR_Q0_TXDP,	"Q0_TXDP",	DUMP_QCU },
-    { AR_Q1_TXDP,	"Q1_TXDP",	DUMP_QCU },
-    { AR_Q2_TXDP,	"Q2_TXDP",	DUMP_QCU },
-    { AR_Q3_TXDP,	"Q3_TXDP",	DUMP_QCU },
-    { AR_Q4_TXDP,	"Q4_TXDP",	DUMP_QCU },
-    { AR_Q5_TXDP,	"Q5_TXDP",	DUMP_QCU },
-    { AR_Q6_TXDP,	"Q6_TXDP",	DUMP_QCU },
-    { AR_Q7_TXDP,	"Q7_TXDP",	DUMP_QCU },
-    { AR_Q8_TXDP,	"Q8_TXDP",	DUMP_QCU },
-    { AR_Q9_TXDP,	"Q9_TXDP",	DUMP_QCU },
-
-    { AR_Q_TXE,		"Q_TXE",	DUMP_QCU },
-    { AR_Q_TXD,		"Q_TXD",	DUMP_QCU },
-
-    { AR_Q0_CBRCFG,	"Q0_CBR",	DUMP_QCU },
-    { AR_Q1_CBRCFG,	"Q1_CBR",	DUMP_QCU },
-    { AR_Q2_CBRCFG,	"Q2_CBR",	DUMP_QCU },
-    { AR_Q3_CBRCFG,	"Q3_CBR",	DUMP_QCU },
-    { AR_Q4_CBRCFG,	"Q4_CBR",	DUMP_QCU },
-    { AR_Q5_CBRCFG,	"Q5_CBR",	DUMP_QCU },
-    { AR_Q6_CBRCFG,	"Q6_CBR",	DUMP_QCU },
-    { AR_Q7_CBRCFG,	"Q7_CBR",	DUMP_QCU },
-    { AR_Q8_CBRCFG,	"Q8_CBR",	DUMP_QCU },
-    { AR_Q9_CBRCFG,	"Q9_CBR",	DUMP_QCU },
-
-    { AR_Q0_RDYTIMECFG,	"Q0_RDYT",	DUMP_QCU },
-    { AR_Q1_RDYTIMECFG,	"Q1_RDYT",	DUMP_QCU },
-    { AR_Q2_RDYTIMECFG,	"Q2_RDYT",	DUMP_QCU },
-    { AR_Q3_RDYTIMECFG,	"Q3_RDYT",	DUMP_QCU },
-    { AR_Q4_RDYTIMECFG,	"Q4_RDYT",	DUMP_QCU },
-    { AR_Q5_RDYTIMECFG,	"Q5_RDYT",	DUMP_QCU },
-    { AR_Q6_RDYTIMECFG,	"Q6_RDYT",	DUMP_QCU },
-    { AR_Q7_RDYTIMECFG,	"Q7_RDYT",	DUMP_QCU },
-    { AR_Q8_RDYTIMECFG,	"Q8_RDYT",	DUMP_QCU },
-    { AR_Q9_RDYTIMECFG,	"Q9_RDYT",	DUMP_QCU },
-
-    { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC",	DUMP_QCU },
-    { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC",	DUMP_QCU },
-
-    { AR_Q0_MISC,	"Q0_MISC",	DUMP_QCU },
-    { AR_Q1_MISC,	"Q1_MISC",	DUMP_QCU },
-    { AR_Q2_MISC,	"Q2_MISC",	DUMP_QCU },
-    { AR_Q3_MISC,	"Q3_MISC",	DUMP_QCU },
-    { AR_Q4_MISC,	"Q4_MISC",	DUMP_QCU },
-    { AR_Q5_MISC,	"Q5_MISC",	DUMP_QCU },
-    { AR_Q6_MISC,	"Q6_MISC",	DUMP_QCU },
-    { AR_Q7_MISC,	"Q7_MISC",	DUMP_QCU },
-    { AR_Q8_MISC,	"Q8_MISC",	DUMP_QCU },
-    { AR_Q9_MISC,	"Q9_MISC",	DUMP_QCU },
-
-    { AR_Q0_STS,	"Q0_STS",	DUMP_QCU },
-    { AR_Q1_STS,	"Q1_STS",	DUMP_QCU },
-    { AR_Q2_STS,	"Q2_STS",	DUMP_QCU },
-    { AR_Q3_STS,	"Q3_STS",	DUMP_QCU },
-    { AR_Q4_STS,	"Q4_STS",	DUMP_QCU },
-    { AR_Q5_STS,	"Q5_STS",	DUMP_QCU },
-    { AR_Q6_STS,	"Q6_STS",	DUMP_QCU },
-    { AR_Q7_STS,	"Q7_STS",	DUMP_QCU },
-    { AR_Q8_STS,	"Q8_STS",	DUMP_QCU },
-    { AR_Q9_STS,	"Q9_STS",	DUMP_QCU },
-
-    { AR_Q_RDYTIMESHDN,	"Q_RDYTIMSHD",	DUMP_QCU },
-
-    { AR_D0_QCUMASK,	"D0_MASK",	DUMP_DCU },
-    { AR_D1_QCUMASK,	"D1_MASK",	DUMP_DCU },
-    { AR_D2_QCUMASK,	"D2_MASK",	DUMP_DCU },
-    { AR_D3_QCUMASK,	"D3_MASK",	DUMP_DCU },
-    { AR_D4_QCUMASK,	"D4_MASK",	DUMP_DCU },
-    { AR_D5_QCUMASK,	"D5_MASK",	DUMP_DCU },
-    { AR_D6_QCUMASK,	"D6_MASK",	DUMP_DCU },
-    { AR_D7_QCUMASK,	"D7_MASK",	DUMP_DCU },
-    { AR_D8_QCUMASK,	"D8_MASK",	DUMP_DCU },
-    { AR_D9_QCUMASK,	"D9_MASK",	DUMP_DCU },
-
-    { AR_D0_LCL_IFS,	"D0_IFS",	DUMP_DCU },
-    { AR_D1_LCL_IFS,	"D1_IFS",	DUMP_DCU },
-    { AR_D2_LCL_IFS,	"D2_IFS",	DUMP_DCU },
-    { AR_D3_LCL_IFS,	"D3_IFS",	DUMP_DCU },
-    { AR_D4_LCL_IFS,	"D4_IFS",	DUMP_DCU },
-    { AR_D5_LCL_IFS,	"D5_IFS",	DUMP_DCU },
-    { AR_D6_LCL_IFS,	"D6_IFS",	DUMP_DCU },
-    { AR_D7_LCL_IFS,	"D7_IFS",	DUMP_DCU },
-    { AR_D8_LCL_IFS,	"D8_IFS",	DUMP_DCU },
-    { AR_D9_LCL_IFS,	"D9_IFS",	DUMP_DCU },
-
-    { AR_D0_RETRY_LIMIT,"D0_RTRY",	DUMP_DCU },
-    { AR_D1_RETRY_LIMIT,"D1_RTRY",	DUMP_DCU },
-    { AR_D2_RETRY_LIMIT,"D2_RTRY",	DUMP_DCU },
-    { AR_D3_RETRY_LIMIT,"D3_RTRY",	DUMP_DCU },
-    { AR_D4_RETRY_LIMIT,"D4_RTRY",	DUMP_DCU },
-    { AR_D5_RETRY_LIMIT,"D5_RTRY",	DUMP_DCU },
-    { AR_D6_RETRY_LIMIT,"D6_RTRY",	DUMP_DCU },
-    { AR_D7_RETRY_LIMIT,"D7_RTRY",	DUMP_DCU },
-    { AR_D8_RETRY_LIMIT,"D8_RTRY",	DUMP_DCU },
-    { AR_D9_RETRY_LIMIT,"D9_RTRY",	DUMP_DCU },
-
-    { AR_D0_CHNTIME,	"D0_CHNT",	DUMP_DCU },
-    { AR_D1_CHNTIME,	"D1_CHNT",	DUMP_DCU },
-    { AR_D2_CHNTIME,	"D2_CHNT",	DUMP_DCU },
-    { AR_D3_CHNTIME,	"D3_CHNT",	DUMP_DCU },
-    { AR_D4_CHNTIME,	"D4_CHNT",	DUMP_DCU },
-    { AR_D5_CHNTIME,	"D5_CHNT",	DUMP_DCU },
-    { AR_D6_CHNTIME,	"D6_CHNT",	DUMP_DCU },
-    { AR_D7_CHNTIME,	"D7_CHNT",	DUMP_DCU },
-    { AR_D8_CHNTIME,	"D8_CHNT",	DUMP_DCU },
-    { AR_D9_CHNTIME,	"D9_CHNT",	DUMP_DCU },
-
-    { AR_D0_MISC,	"D0_MISC",	DUMP_DCU },
-    { AR_D1_MISC,	"D1_MISC",	DUMP_DCU },
-    { AR_D2_MISC,	"D2_MISC",	DUMP_DCU },
-    { AR_D3_MISC,	"D3_MISC",	DUMP_DCU },
-    { AR_D4_MISC,	"D4_MISC",	DUMP_DCU },
-    { AR_D5_MISC,	"D5_MISC",	DUMP_DCU },
-    { AR_D6_MISC,	"D6_MISC",	DUMP_DCU },
-    { AR_D7_MISC,	"D7_MISC",	DUMP_DCU },
-    { AR_D8_MISC,	"D8_MISC",	DUMP_DCU },
-    { AR_D9_MISC,	"D9_MISC",	DUMP_DCU },
-
-    { AR_D0_SEQNUM,	"D0_SEQ",	DUMP_DCU },
-    { AR_D1_SEQNUM,	"D1_SEQ",	DUMP_DCU },
-    { AR_D2_SEQNUM,	"D2_SEQ",	DUMP_DCU },
-    { AR_D3_SEQNUM,	"D3_SEQ",	DUMP_DCU },
-    { AR_D4_SEQNUM,	"D4_SEQ",	DUMP_DCU },
-    { AR_D5_SEQNUM,	"D5_SEQ",	DUMP_DCU },
-    { AR_D6_SEQNUM,	"D6_SEQ",	DUMP_DCU },
-    { AR_D7_SEQNUM,	"D7_SEQ",	DUMP_DCU },
-    { AR_D8_SEQNUM,	"D8_SEQ",	DUMP_DCU },
-    { AR_D9_SEQNUM,	"D9_SEQ",	DUMP_DCU },
-
-    { AR_D_GBL_IFS_SIFS,"D_SIFS",	DUMP_BASIC },
-    { AR_D_GBL_IFS_SLOT,"D_SLOT",	DUMP_BASIC },
-    { AR_D_GBL_IFS_EIFS,"D_EIFS",	DUMP_BASIC },
-    { AR_D_GBL_IFS_MISC,"D_MISC",	DUMP_BASIC },
-    { AR_D_FPCTL,	"D_FPCTL",	DUMP_BASIC },
-    { AR_D_TXPSE,	"D_TXPSE",	DUMP_BASIC },
-#if 0
-    { AR_D_TXBLK_CMD,	"D_CMD",	DUMP_BASIC },
-    { AR_D_TXBLK_DATA,	"D_DATA",	DUMP_BASIC },
-    { AR_D_TXBLK_CLR,	"D_CLR",	DUMP_BASIC },
-    { AR_D_TXBLK_SET,	"D_SET",	DUMP_BASIC },
-#endif
-    { AR_RC,		"RC",		DUMP_BASIC },
-    { AR_SCR,		"SCR",		DUMP_BASIC },
-    { AR_INTPEND,	"INTPEND",	DUMP_BASIC },
-    { AR_SFR,		"SFR",		DUMP_BASIC },
-    { AR_PCICFG,	"PCICFG",	DUMP_BASIC },
-    { AR_GPIOCR,	"GPIOCR",	DUMP_BASIC },
-    { AR_GPIODO,	"GPIODO",	DUMP_BASIC },
-    { AR_GPIODI,	"GPIODI",	DUMP_BASIC },
-    { AR_SREV,		"SREV",		DUMP_BASIC },
+    DEFVOID(AR_ISR_RAC,		"ISR_RAC"),
+    DEFINT(AR_ISR_S0_S,		"ISR_S0_S"),
+    DEFINT(AR_ISR_S1_S,		"ISR_S1_S"),
+    DEFINT(AR_ISR_S2_S,		"ISR_S2_S"),
+    DEFINT(AR_ISR_S3_S,		"ISR_S3_S"),
+    DEFINT(AR_ISR_S4_S,		"ISR_S4_S"),
+
+    DEFQCU(AR_Q0_TXDP,		"Q0_TXDP"),
+    DEFQCU(AR_Q1_TXDP,		"Q1_TXDP"),
+    DEFQCU(AR_Q2_TXDP,		"Q2_TXDP"),
+    DEFQCU(AR_Q3_TXDP,		"Q3_TXDP"),
+    DEFQCU(AR_Q4_TXDP,		"Q4_TXDP"),
+    DEFQCU(AR_Q5_TXDP,		"Q5_TXDP"),
+    DEFQCU(AR_Q6_TXDP,		"Q6_TXDP"),
+    DEFQCU(AR_Q7_TXDP,		"Q7_TXDP"),
+    DEFQCU(AR_Q8_TXDP,		"Q8_TXDP"),
+    DEFQCU(AR_Q9_TXDP,		"Q9_TXDP"),
+
+    DEFQCU(AR_Q_TXE,		"Q_TXE"),
+    DEFQCU(AR_Q_TXD,		"Q_TXD"),
+
+    DEFQCU(AR_Q0_CBRCFG,	"Q0_CBR"),
+    DEFQCU(AR_Q1_CBRCFG,	"Q1_CBR"),
+    DEFQCU(AR_Q2_CBRCFG,	"Q2_CBR"),
+    DEFQCU(AR_Q3_CBRCFG,	"Q3_CBR"),
+    DEFQCU(AR_Q4_CBRCFG,	"Q4_CBR"),
+    DEFQCU(AR_Q5_CBRCFG,	"Q5_CBR"),
+    DEFQCU(AR_Q6_CBRCFG,	"Q6_CBR"),
+    DEFQCU(AR_Q7_CBRCFG,	"Q7_CBR"),
+    DEFQCU(AR_Q8_CBRCFG,	"Q8_CBR"),
+    DEFQCU(AR_Q9_CBRCFG,	"Q9_CBR"),
+
+    DEFQCU(AR_Q0_RDYTIMECFG,	"Q0_RDYT"),
+    DEFQCU(AR_Q1_RDYTIMECFG,	"Q1_RDYT"),
+    DEFQCU(AR_Q2_RDYTIMECFG,	"Q2_RDYT"),
+    DEFQCU(AR_Q3_RDYTIMECFG,	"Q3_RDYT"),
+    DEFQCU(AR_Q4_RDYTIMECFG,	"Q4_RDYT"),
+    DEFQCU(AR_Q5_RDYTIMECFG,	"Q5_RDYT"),
+    DEFQCU(AR_Q6_RDYTIMECFG,	"Q6_RDYT"),
+    DEFQCU(AR_Q7_RDYTIMECFG,	"Q7_RDYT"),
+    DEFQCU(AR_Q8_RDYTIMECFG,	"Q8_RDYT"),
+    DEFQCU(AR_Q9_RDYTIMECFG,	"Q9_RDYT"),
+
+    DEFQCU(AR_Q_ONESHOTARM_SC,	"Q_ONESHOTARM_SC"),
+    DEFQCU(AR_Q_ONESHOTARM_CC,	"Q_ONESHOTARM_CC"),
+
+    DEFQCU(AR_Q0_MISC,		"Q0_MISC"),
+    DEFQCU(AR_Q1_MISC,		"Q1_MISC"),
+    DEFQCU(AR_Q2_MISC,		"Q2_MISC"),
+    DEFQCU(AR_Q3_MISC,		"Q3_MISC"),
+    DEFQCU(AR_Q4_MISC,		"Q4_MISC"),
+    DEFQCU(AR_Q5_MISC,		"Q5_MISC"),
+    DEFQCU(AR_Q6_MISC,		"Q6_MISC"),
+    DEFQCU(AR_Q7_MISC,		"Q7_MISC"),
+    DEFQCU(AR_Q8_MISC,		"Q8_MISC"),
+    DEFQCU(AR_Q9_MISC,		"Q9_MISC"),
+
+    DEFQCU(AR_Q0_STS,		"Q0_STS"),
+    DEFQCU(AR_Q1_STS,		"Q1_STS"),
+    DEFQCU(AR_Q2_STS,		"Q2_STS"),
+    DEFQCU(AR_Q3_STS,		"Q3_STS"),
+    DEFQCU(AR_Q4_STS,		"Q4_STS"),
+    DEFQCU(AR_Q5_STS,		"Q5_STS"),
+    DEFQCU(AR_Q6_STS,		"Q6_STS"),
+    DEFQCU(AR_Q7_STS,		"Q7_STS"),
+    DEFQCU(AR_Q8_STS,		"Q8_STS"),
+    DEFQCU(AR_Q9_STS,		"Q9_STS"),
+
+    DEFQCU(AR_Q_RDYTIMESHDN,	"Q_RDYTIMSHD"),
+
+    DEFQCU(AR_D0_QCUMASK,	"D0_MASK"),
+    DEFQCU(AR_D1_QCUMASK,	"D1_MASK"),
+    DEFQCU(AR_D2_QCUMASK,	"D2_MASK"),
+    DEFQCU(AR_D3_QCUMASK,	"D3_MASK"),
+    DEFQCU(AR_D4_QCUMASK,	"D4_MASK"),
+    DEFQCU(AR_D5_QCUMASK,	"D5_MASK"),
+    DEFQCU(AR_D6_QCUMASK,	"D6_MASK"),
+    DEFQCU(AR_D7_QCUMASK,	"D7_MASK"),
+    DEFQCU(AR_D8_QCUMASK,	"D8_MASK"),
+    DEFQCU(AR_D9_QCUMASK,	"D9_MASK"),
+
+    DEFDCU(AR_D0_LCL_IFS,	"D0_IFS"),
+    DEFDCU(AR_D1_LCL_IFS,	"D1_IFS"),
+    DEFDCU(AR_D2_LCL_IFS,	"D2_IFS"),
+    DEFDCU(AR_D3_LCL_IFS,	"D3_IFS"),
+    DEFDCU(AR_D4_LCL_IFS,	"D4_IFS"),
+    DEFDCU(AR_D5_LCL_IFS,	"D5_IFS"),
+    DEFDCU(AR_D6_LCL_IFS,	"D6_IFS"),
+    DEFDCU(AR_D7_LCL_IFS,	"D7_IFS"),
+    DEFDCU(AR_D8_LCL_IFS,	"D8_IFS"),
+    DEFDCU(AR_D9_LCL_IFS,	"D9_IFS"),
+
+    DEFDCU(AR_D0_RETRY_LIMIT,	"D0_RTRY"),
+    DEFDCU(AR_D1_RETRY_LIMIT,	"D1_RTRY"),
+    DEFDCU(AR_D2_RETRY_LIMIT,	"D2_RTRY"),
+    DEFDCU(AR_D3_RETRY_LIMIT,	"D3_RTRY"),
+    DEFDCU(AR_D4_RETRY_LIMIT,	"D4_RTRY"),
+    DEFDCU(AR_D5_RETRY_LIMIT,	"D5_RTRY"),
+    DEFDCU(AR_D6_RETRY_LIMIT,	"D6_RTRY"),
+    DEFDCU(AR_D7_RETRY_LIMIT,	"D7_RTRY"),
+    DEFDCU(AR_D8_RETRY_LIMIT,	"D8_RTRY"),
+    DEFDCU(AR_D9_RETRY_LIMIT,	"D9_RTRY"),
+
+    DEFDCU(AR_D0_CHNTIME,	"D0_CHNT"),
+    DEFDCU(AR_D1_CHNTIME,	"D1_CHNT"),
+    DEFDCU(AR_D2_CHNTIME,	"D2_CHNT"),
+    DEFDCU(AR_D3_CHNTIME,	"D3_CHNT"),
+    DEFDCU(AR_D4_CHNTIME,	"D4_CHNT"),
+    DEFDCU(AR_D5_CHNTIME,	"D5_CHNT"),
+    DEFDCU(AR_D6_CHNTIME,	"D6_CHNT"),
+    DEFDCU(AR_D7_CHNTIME,	"D7_CHNT"),
+    DEFDCU(AR_D8_CHNTIME,	"D8_CHNT"),
+    DEFDCU(AR_D9_CHNTIME,	"D9_CHNT"),
+
+    DEFDCU(AR_D0_MISC,		"D0_MISC"),
+    DEFDCU(AR_D1_MISC,		"D1_MISC"),
+    DEFDCU(AR_D2_MISC,		"D2_MISC"),
+    DEFDCU(AR_D3_MISC,		"D3_MISC"),
+    DEFDCU(AR_D4_MISC,		"D4_MISC"),
+    DEFDCU(AR_D5_MISC,		"D5_MISC"),
+    DEFDCU(AR_D6_MISC,		"D6_MISC"),
+    DEFDCU(AR_D7_MISC,		"D7_MISC"),
+    DEFDCU(AR_D8_MISC,		"D8_MISC"),
+    DEFDCU(AR_D9_MISC,		"D9_MISC"),
+
+    DEFDCU(AR_D0_SEQNUM,	"D0_SEQ"),
+    DEFDCU(AR_D1_SEQNUM,	"D1_SEQ"),
+    DEFDCU(AR_D2_SEQNUM,	"D2_SEQ"),
+    DEFDCU(AR_D3_SEQNUM,	"D3_SEQ"),
+    DEFDCU(AR_D4_SEQNUM,	"D4_SEQ"),
+    DEFDCU(AR_D5_SEQNUM,	"D5_SEQ"),
+    DEFDCU(AR_D6_SEQNUM,	"D6_SEQ"),
+    DEFDCU(AR_D7_SEQNUM,	"D7_SEQ"),
+    DEFDCU(AR_D8_SEQNUM,	"D8_SEQ"),
+    DEFDCU(AR_D9_SEQNUM,	"D9_SEQ"),
+
+    DEFBASIC(AR_D_GBL_IFS_SIFS,	"D_SIFS"),
+    DEFBASIC(AR_D_GBL_IFS_SLOT,	"D_SLOT"),
+    DEFBASIC(AR_D_GBL_IFS_EIFS,	"D_EIFS"),
+    DEFBASIC(AR_D_GBL_IFS_MISC,	"D_MISC"),
+    DEFBASIC(AR_D_FPCTL,	"D_FPCTL"),
+    DEFBASIC(AR_D_TXPSE,	"D_TXPSE"),
+    DEFVOID(AR_D_TXBLK_CMD,	"D_CMD"),
 #if 0
-    { AR_EEPROM_ADDR,	"EEADDR",	DUMP_BASIC },
-    { AR_EEPROM_DATA,	"EEDATA",	DUMP_BASIC },
-    { AR_EEPROM_CMD,	"EECMD",	DUMP_BASIC },
-    { AR_EEPROM_STS,	"EESTS",	DUMP_BASIC },
-    { AR_EEPROM_CFG,	"EECFG",	DUMP_BASIC },
+    DEFVOID(AR_D_TXBLK_DATA,	"D_DATA"),
 #endif
-    { AR_STA_ID0,	"STA_ID0",	DUMP_BASIC },
-    { AR_STA_ID1,	"STA_ID1",	DUMP_BASIC },
-    { AR_BSS_ID0,	"BSS_ID0",	DUMP_BASIC },
-    { AR_BSS_ID1,	"BSS_ID1",	DUMP_BASIC },
-    { AR_SLOT_TIME,	"SLOTTIME",	DUMP_BASIC },
-    { AR_TIME_OUT,	"TIME_OUT",	DUMP_BASIC },
-    { AR_RSSI_THR,	"RSSI_THR",	DUMP_BASIC },
-    { AR_USEC,		"USEC",		DUMP_BASIC },
-    { AR_BEACON,	"BEACON",	DUMP_BASIC },
-    { AR_CFP_PERIOD,	"CFP_PER",	DUMP_BASIC },
-    { AR_TIMER0,	"TIMER0",	DUMP_BASIC },
-    { AR_TIMER1,	"TIMER1",	DUMP_BASIC },
-    { AR_TIMER2,	"TIMER2",	DUMP_BASIC },
-    { AR_TIMER3,	"TIMER3",	DUMP_BASIC },
-    { AR_CFP_DUR,	"CFP_DUR",	DUMP_BASIC },
-    { AR_RX_FILTER,	"RXFILTER",	DUMP_BASIC },
-    { AR_MCAST_FIL0,	"MCAST_0",	DUMP_BASIC },
-    { AR_MCAST_FIL1,	"MCAST_1",	DUMP_BASIC },
-    { AR_DIAG_SW,	"DIAG_SW",	DUMP_BASIC },
-    { AR_TSF_L32,	"TSF_L32",	DUMP_BASIC },
-    { AR_TSF_U32,	"TSF_U32",	DUMP_BASIC },
-    { AR_TST_ADDAC,	"TST_ADAC",	DUMP_BASIC },
-    { AR_DEF_ANTENNA,	"DEF_ANT",	DUMP_BASIC },
-
-    { AR_LAST_TSTP,	"LAST_TST",	DUMP_BASIC },
-    { AR_NAV,		"NAV",		DUMP_BASIC },
-    { AR_RTS_OK,	"RTS_OK",	DUMP_BASIC },
-    { AR_RTS_FAIL,	"RTS_FAIL",	DUMP_BASIC },
-    { AR_ACK_FAIL,	"ACK_FAIL",	DUMP_BASIC },
-    { AR_FCS_FAIL,	"FCS_FAIL",	DUMP_BASIC },
-    { AR_BEACON_CNT,	"BEAC_CNT",	DUMP_BASIC },
+    DEFVOID(AR_D_TXBLK_CLR,	"D_CLR"),
+    DEFVOID(AR_D_TXBLK_SET,	"D_SET"),
+    DEFBASICfmt(AR_RC,		"RC",		AR_RC_BITS),
+    DEFBASICfmt(AR_SCR,		"SCR",		AR_SCR_BITS),
+    DEFBASICfmt(AR_INTPEND,	"INTPEND",	AR_INTPEND_BITS),
+    DEFBASIC(AR_SFR,		"SFR"),
+    DEFBASICfmt(AR_PCICFG,	"PCICFG",	AR_PCICFG_BITS),
+    DEFBASIC(AR_GPIOCR,		"GPIOCR"),
+    DEFBASIC(AR_GPIODO,		"GPIODO"),
+    DEFBASIC(AR_GPIODI,		"GPIODI"),
+    DEFBASIC(AR_SREV,		"SREV"),
+    DEFVOID(AR_EEPROM_ADDR,	"EEADDR"),
+    DEFVOID(AR_EEPROM_DATA,	"EEDATA"),
+    DEFVOID(AR_EEPROM_CMD,	"EECMD"),
+    DEFVOID(AR_EEPROM_STS,	"EESTS"),
+    DEFVOID(AR_EEPROM_CFG,	"EECFG"),
+    DEFBASIC(AR_STA_ID0,	"STA_ID0"),
+    DEFBASICfmt(AR_STA_ID1,	"STA_ID1",	AR_STA_ID1_BITS),
+    DEFBASIC(AR_BSS_ID0,	"BSS_ID0"),
+    DEFBASIC(AR_BSS_ID1,	"BSS_ID1"),
+    DEFBASIC(AR_SLOT_TIME,	"SLOTTIME"),
+    DEFBASIC(AR_TIME_OUT,	"TIME_OUT"),
+    DEFBASIC(AR_RSSI_THR,	"RSSI_THR"),
+    DEFBASIC(AR_USEC,		"USEC"),
+    DEFBASICfmt(AR_BEACON,	"BEACON",	AR_BEACON_BITS),
+    DEFBASIC(AR_CFP_PERIOD,	"CFP_PER"),
+    DEFBASIC(AR_TIMER0,		"TIMER0"),
+    DEFBASIC(AR_TIMER1,		"TIMER1"),
+    DEFBASIC(AR_TIMER2,		"TIMER2"),
+    DEFBASIC(AR_TIMER3,		"TIMER3"),
+    DEFBASIC(AR_CFP_DUR,	"CFP_DUR"),
+    DEFBASICfmt(AR_RX_FILTER,	"RXFILTER",	AR_RX_FILTER_BITS),
+    DEFBASIC(AR_MCAST_FIL0,	"MCAST_0"),
+    DEFBASIC(AR_MCAST_FIL1,	"MCAST_1"),
+    DEFBASICfmt(AR_DIAG_SW,	"DIAG_SW",	AR_DIAG_SW_BITS),
+    DEFBASIC(AR_TSF_L32,	"TSF_L32"),
+    DEFBASIC(AR_TSF_U32,	"TSF_U32"),
+    DEFBASIC(AR_TST_ADDAC,	"TST_ADAC"),
+    DEFBASIC(AR_DEF_ANTENNA,	"DEF_ANT"),
+
+    DEFBASIC(AR_LAST_TSTP,	"LAST_TST"),
+    DEFBASIC(AR_NAV,		"NAV"),
+    DEFBASIC(AR_RTS_OK,		"RTS_OK"),
+    DEFBASIC(AR_RTS_FAIL,	"RTS_FAIL"),
+    DEFBASIC(AR_ACK_FAIL,	"ACK_FAIL"),
+    DEFBASIC(AR_FCS_FAIL,	"FCS_FAIL"),
+    DEFBASIC(AR_BEACON_CNT,	"BEAC_CNT"),
+
+    DEFVOID(AR_PHY_TURBO,	"PHY_TURBO"),
+    DEFVOID(AR_PHY_CHIP_ID,	"PHY_CHIP_ID"),
+    DEFVOID(AR_PHY_ACTIVE,	"PHY_ACTIVE"),
+    DEFVOID(AR_PHY_AGC_CONTROL,	"PHY_AGC_CONTROL"),
+    DEFVOID(AR_PHY_PLL_CTL,	"PHY_PLL_CTL"),
+    DEFVOID(AR_PHY_RX_DELAY,	"PHY_RX_DELAY"),
+    DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"),
+    DEFVOID(AR_PHY_RADAR_0,	"PHY_RADAR_0"),
+    DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I,"PHY_IQCAL_RES_PWR_MEAS_I"),
+    DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q,"PHY_IQCAL_RES_PWR_MEAS_Q"),
+    DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS,"PHY_IQCAL_RES_IQ_CORR_MEAS"),
+    DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"),
+    DEFVOID(AR5211_PHY_MODE,	"PHY_MODE"),
 };
 
 static __constructor void

Modified: head/tools/tools/ath/athregs/dumpregs_5212.c
==============================================================================
--- head/tools/tools/ath/athregs/dumpregs_5212.c	Wed Mar 11 16:32:00 2009	(r189700)
+++ head/tools/tools/ath/athregs/dumpregs_5212.c	Wed Mar 11 17:14:17 2009	(r189701)
@@ -43,279 +43,376 @@
 #define	MAC5213	SREV(5,9), SREV(16,0)
 
 static struct dumpreg ar5212regs[] = {
-    { AR_CR,		"CR",		DUMP_BASIC },
-    { AR_RXDP,		"RXDP",		DUMP_BASIC },
-    { AR_CFG,		"CFG",		DUMP_BASIC },
-    { AR_IER,		"IER",		DUMP_BASIC },
-    { AR_TXCFG,		"TXCFG",	DUMP_BASIC },
-    { AR_RXCFG,		"RXCFG",	DUMP_BASIC },
-    { AR_MIBC,		"MIBC",		DUMP_BASIC },
-    { AR_TOPS,		"TOPS",		DUMP_BASIC },
-    { AR_RXNPTO,	"RXNPTO",	DUMP_BASIC },
-    { AR_TXNPTO,	"TXNPTO",	DUMP_BASIC },
-    { AR_RPGTO,		"RPGTO",	DUMP_BASIC },
-    { AR_RPCNT,		"RPCNT",	DUMP_BASIC },
-    { AR_MACMISC,	"MACMISC",	DUMP_BASIC },
-    { AR_SPC_0,		"SPC_0",	DUMP_BASIC },
-    { AR_SPC_1,		"SPC_1",	DUMP_BASIC },
-
-    { AR_ISR,		"ISR",		DUMP_INTERRUPT },
-    { AR_ISR_S0,	"ISR_S0",	DUMP_INTERRUPT },
-    { AR_ISR_S1,	"ISR_S1",	DUMP_INTERRUPT },
-    { AR_ISR_S2,	"ISR_S2",	DUMP_INTERRUPT },
-    { AR_ISR_S3,	"ISR_S3",	DUMP_INTERRUPT },
-    { AR_ISR_S4,	"ISR_S4",	DUMP_INTERRUPT },
-    { AR_IMR,		"IMR",		DUMP_INTERRUPT },
-    { AR_IMR_S0,	"IMR_S0",	DUMP_INTERRUPT },
-    { AR_IMR_S1,	"IMR_S1",	DUMP_INTERRUPT },
-    { AR_IMR_S2,	"IMR_S2",	DUMP_INTERRUPT },
-    { AR_IMR_S3,	"IMR_S3",	DUMP_INTERRUPT },
-    { AR_IMR_S4,	"IMR_S4",	DUMP_INTERRUPT },
-#if 0
+    DEFBASIC(AR_CR,		"CR"),
+    DEFBASIC(AR_RXDP,		"RXDP"),
+    DEFBASICfmt(AR_CFG,		"CFG",
+	   "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\6AP_ADHOC\11PHOK\12EEBS"),
+    DEFBASIC(AR_IER,		"IER"),
+    DEFBASIC(AR_TXCFG,		"TXCFG"),
+    DEFBASICfmt(AR_RXCFG,	"RXCFG",
+	  "\20\6JUMBO_ENA\7JUMBO_WRAP\10SLEEP_DEBUG"),
+    DEFBASIC(AR_MIBC,		"MIBC"),
+    DEFBASIC(AR_TOPS,		"TOPS"),
+    DEFBASIC(AR_RXNPTO,		"RXNPTO"),
+    DEFBASIC(AR_TXNPTO,		"TXNPTO"),
+    DEFBASIC(AR_RPGTO,		"RPGTO"),
+    DEFBASIC(AR_RPCNT,		"RPCNT"),
+    DEFBASIC(AR_MACMISC,	"MACMISC"),
+    DEFBASIC(AR_SPC_0,		"SPC_0"),
+    DEFBASIC(AR_SPC_1,		"SPC_1"),
+
+    DEFINTfmt(AR_ISR,		"ISR",
+	  "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
+	  "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
+	  "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
+	  "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
+    DEFINT(AR_ISR_S0,		"ISR_S0"),
+    DEFINT(AR_ISR_S1,		"ISR_S1"),
+    DEFINTfmt(AR_ISR_S2,	"ISR_S2",
+	  "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
+	  "\30CABTO\31DTIM"),
+    DEFINT(AR_ISR_S3,		"ISR_S3"),
+    DEFINT(AR_ISR_S4,		"ISR_S4"),
+    DEFINTfmt(AR_IMR,		"IMR",
+	  "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC"
+	  "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"
+	  "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS"
+	  "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"),
+    DEFINT(AR_IMR_S0,		"IMR_S0"),
+    DEFINT(AR_IMR_S1,		"IMR_S1"),
+    DEFINTfmt(AR_IMR_S2,	"IMR_S2",
+	  "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO"
+	  "\30CABTO\31DTIM"),
+    DEFINT(AR_IMR_S3,		"IMR_S3"),
+    DEFINT(AR_IMR_S4,		"IMR_S4"),
     /* NB: don't read the RAC so we don't affect operation */
-    { AR_ISR_RAC,	"ISR_RAC",	DUMP_INTERRUPT },
-#endif
-    { AR_ISR_S0_S,	"ISR_S0_S",	DUMP_INTERRUPT },
-    { AR_ISR_S1_S,	"ISR_S1_S",	DUMP_INTERRUPT },
-    { AR_ISR_S2_S,	"ISR_S2_S",	DUMP_INTERRUPT },
-    { AR_ISR_S3_S,	"ISR_S3_S",	DUMP_INTERRUPT },
-    { AR_ISR_S4_S,	"ISR_S4_S",	DUMP_INTERRUPT },
-
-    { AR_DMADBG_0,	"DMADBG0",	DUMP_BASIC },
-    { AR_DMADBG_1,	"DMADBG1",	DUMP_BASIC },
-    { AR_DMADBG_2,	"DMADBG2",	DUMP_BASIC },
-    { AR_DMADBG_3,	"DMADBG3",	DUMP_BASIC },
-    { AR_DMADBG_4,	"DMADBG4",	DUMP_BASIC },
-    { AR_DMADBG_5,	"DMADBG5",	DUMP_BASIC },
-    { AR_DMADBG_6,	"DMADBG6",	DUMP_BASIC },
-    { AR_DMADBG_7,	"DMADBG7",	DUMP_BASIC },
-
-    { AR_DCM_A,		"DCM_A",	DUMP_BASIC },
-    { AR_DCM_D,		"DCM_D",	DUMP_BASIC },
-    { AR_DCCFG,		"DCCFG",	DUMP_BASIC },
-    { AR_CCFG,		"CCFG",		DUMP_BASIC },
-    { AR_CCUCFG,	"CCUCFG",	DUMP_BASIC },
-    { AR_CPC_0,		"CPC0",		DUMP_BASIC },
-    { AR_CPC_1,		"CPC1",		DUMP_BASIC },
-    { AR_CPC_2,		"CPC2",		DUMP_BASIC },
-    { AR_CPC_3,		"CPC3",		DUMP_BASIC },
-    { AR_CPCOVF,	"CPCOVF",	DUMP_BASIC },
-
-    { AR_Q0_TXDP,	"Q0_TXDP",	DUMP_QCU },
-    { AR_Q1_TXDP,	"Q1_TXDP",	DUMP_QCU },
-    { AR_Q2_TXDP,	"Q2_TXDP",	DUMP_QCU },
-    { AR_Q3_TXDP,	"Q3_TXDP",	DUMP_QCU },
-    { AR_Q4_TXDP,	"Q4_TXDP",	DUMP_QCU },
-    { AR_Q5_TXDP,	"Q5_TXDP",	DUMP_QCU },
-    { AR_Q6_TXDP,	"Q6_TXDP",	DUMP_QCU },
-    { AR_Q7_TXDP,	"Q7_TXDP",	DUMP_QCU },
-    { AR_Q8_TXDP,	"Q8_TXDP",	DUMP_QCU },
-    { AR_Q9_TXDP,	"Q9_TXDP",	DUMP_QCU },
-
-    { AR_Q_TXE,		"Q_TXE",	DUMP_QCU },
-    { AR_Q_TXD,		"Q_TXD",	DUMP_QCU },
-
-    { AR_Q0_CBRCFG,	"Q0_CBR",	DUMP_QCU },
-    { AR_Q1_CBRCFG,	"Q1_CBR",	DUMP_QCU },
-    { AR_Q2_CBRCFG,	"Q2_CBR",	DUMP_QCU },
-    { AR_Q3_CBRCFG,	"Q3_CBR",	DUMP_QCU },
-    { AR_Q4_CBRCFG,	"Q4_CBR",	DUMP_QCU },
-    { AR_Q5_CBRCFG,	"Q5_CBR",	DUMP_QCU },
-    { AR_Q6_CBRCFG,	"Q6_CBR",	DUMP_QCU },
-    { AR_Q7_CBRCFG,	"Q7_CBR",	DUMP_QCU },
-    { AR_Q8_CBRCFG,	"Q8_CBR",	DUMP_QCU },
-    { AR_Q9_CBRCFG,	"Q9_CBR",	DUMP_QCU },
-
-    { AR_Q0_RDYTIMECFG,	"Q0_RDYT",	DUMP_QCU },
-    { AR_Q1_RDYTIMECFG,	"Q1_RDYT",	DUMP_QCU },
-    { AR_Q2_RDYTIMECFG,	"Q2_RDYT",	DUMP_QCU },
-    { AR_Q3_RDYTIMECFG,	"Q3_RDYT",	DUMP_QCU },
-    { AR_Q4_RDYTIMECFG,	"Q4_RDYT",	DUMP_QCU },
-    { AR_Q5_RDYTIMECFG,	"Q5_RDYT",	DUMP_QCU },
-    { AR_Q6_RDYTIMECFG,	"Q6_RDYT",	DUMP_QCU },
-    { AR_Q7_RDYTIMECFG,	"Q7_RDYT",	DUMP_QCU },
-    { AR_Q8_RDYTIMECFG,	"Q8_RDYT",	DUMP_QCU },
-    { AR_Q9_RDYTIMECFG,	"Q9_RDYT",	DUMP_QCU },
-
-    { AR_Q_ONESHOTARM_SC,"Q_ONESHOTARM_SC",	DUMP_QCU },
-    { AR_Q_ONESHOTARM_CC,"Q_ONESHOTARM_CC",	DUMP_QCU },
-
-    { AR_Q0_MISC,	"Q0_MISC",	DUMP_QCU },
-    { AR_Q1_MISC,	"Q1_MISC",	DUMP_QCU },
-    { AR_Q2_MISC,	"Q2_MISC",	DUMP_QCU },
-    { AR_Q3_MISC,	"Q3_MISC",	DUMP_QCU },
-    { AR_Q4_MISC,	"Q4_MISC",	DUMP_QCU },
-    { AR_Q5_MISC,	"Q5_MISC",	DUMP_QCU },
-    { AR_Q6_MISC,	"Q6_MISC",	DUMP_QCU },
-    { AR_Q7_MISC,	"Q7_MISC",	DUMP_QCU },
-    { AR_Q8_MISC,	"Q8_MISC",	DUMP_QCU },
-    { AR_Q9_MISC,	"Q9_MISC",	DUMP_QCU },
-
-    { AR_Q0_STS,	"Q0_STS",	DUMP_QCU },
-    { AR_Q1_STS,	"Q1_STS",	DUMP_QCU },
-    { AR_Q2_STS,	"Q2_STS",	DUMP_QCU },
-    { AR_Q3_STS,	"Q3_STS",	DUMP_QCU },
-    { AR_Q4_STS,	"Q4_STS",	DUMP_QCU },
-    { AR_Q5_STS,	"Q5_STS",	DUMP_QCU },
-    { AR_Q6_STS,	"Q6_STS",	DUMP_QCU },
-    { AR_Q7_STS,	"Q7_STS",	DUMP_QCU },
-    { AR_Q8_STS,	"Q8_STS",	DUMP_QCU },
-    { AR_Q9_STS,	"Q9_STS",	DUMP_QCU },
-
-    { AR_Q_RDYTIMESHDN,	"Q_RDYTIMSHD",	DUMP_QCU },
-
-    { AR_Q_CBBS,	"Q_CBBS",	DUMP_QCU },
-    { AR_Q_CBBA,	"Q_CBBA",	DUMP_QCU },
-    { AR_Q_CBC,		"Q_CBC",	DUMP_QCU },
-
-    { AR_D0_QCUMASK,	"D0_MASK",	DUMP_DCU },
-    { AR_D1_QCUMASK,	"D1_MASK",	DUMP_DCU },
-    { AR_D2_QCUMASK,	"D2_MASK",	DUMP_DCU },
-    { AR_D3_QCUMASK,	"D3_MASK",	DUMP_DCU },
-    { AR_D4_QCUMASK,	"D4_MASK",	DUMP_DCU },
-    { AR_D5_QCUMASK,	"D5_MASK",	DUMP_DCU },
-    { AR_D6_QCUMASK,	"D6_MASK",	DUMP_DCU },
-    { AR_D7_QCUMASK,	"D7_MASK",	DUMP_DCU },
-    { AR_D8_QCUMASK,	"D8_MASK",	DUMP_DCU },
-    { AR_D9_QCUMASK,	"D9_MASK",	DUMP_DCU },
-
-    { AR_D0_LCL_IFS,	"D0_IFS",	DUMP_DCU },
-    { AR_D1_LCL_IFS,	"D1_IFS",	DUMP_DCU },
-    { AR_D2_LCL_IFS,	"D2_IFS",	DUMP_DCU },
-    { AR_D3_LCL_IFS,	"D3_IFS",	DUMP_DCU },
-    { AR_D4_LCL_IFS,	"D4_IFS",	DUMP_DCU },
-    { AR_D5_LCL_IFS,	"D5_IFS",	DUMP_DCU },
-    { AR_D6_LCL_IFS,	"D6_IFS",	DUMP_DCU },
-    { AR_D7_LCL_IFS,	"D7_IFS",	DUMP_DCU },
-    { AR_D8_LCL_IFS,	"D8_IFS",	DUMP_DCU },
-    { AR_D9_LCL_IFS,	"D9_IFS",	DUMP_DCU },
-
-    { AR_D0_RETRY_LIMIT,"D0_RTRY",	DUMP_DCU },
-    { AR_D1_RETRY_LIMIT,"D1_RTRY",	DUMP_DCU },
-    { AR_D2_RETRY_LIMIT,"D2_RTRY",	DUMP_DCU },
-    { AR_D3_RETRY_LIMIT,"D3_RTRY",	DUMP_DCU },
-    { AR_D4_RETRY_LIMIT,"D4_RTRY",	DUMP_DCU },
-    { AR_D5_RETRY_LIMIT,"D5_RTRY",	DUMP_DCU },
-    { AR_D6_RETRY_LIMIT,"D6_RTRY",	DUMP_DCU },
-    { AR_D7_RETRY_LIMIT,"D7_RTRY",	DUMP_DCU },
-    { AR_D8_RETRY_LIMIT,"D8_RTRY",	DUMP_DCU },
-    { AR_D9_RETRY_LIMIT,"D9_RTRY",	DUMP_DCU },
-
-    { AR_D0_CHNTIME,	"D0_CHNT",	DUMP_DCU },
-    { AR_D1_CHNTIME,	"D1_CHNT",	DUMP_DCU },
-    { AR_D2_CHNTIME,	"D2_CHNT",	DUMP_DCU },
-    { AR_D3_CHNTIME,	"D3_CHNT",	DUMP_DCU },
-    { AR_D4_CHNTIME,	"D4_CHNT",	DUMP_DCU },
-    { AR_D5_CHNTIME,	"D5_CHNT",	DUMP_DCU },
-    { AR_D6_CHNTIME,	"D6_CHNT",	DUMP_DCU },
-    { AR_D7_CHNTIME,	"D7_CHNT",	DUMP_DCU },
-    { AR_D8_CHNTIME,	"D8_CHNT",	DUMP_DCU },
-    { AR_D9_CHNTIME,	"D9_CHNT",	DUMP_DCU },
-
-    { AR_D0_MISC,	"D0_MISC",	DUMP_DCU },
-    { AR_D1_MISC,	"D1_MISC",	DUMP_DCU },
-    { AR_D2_MISC,	"D2_MISC",	DUMP_DCU },
-    { AR_D3_MISC,	"D3_MISC",	DUMP_DCU },
-    { AR_D4_MISC,	"D4_MISC",	DUMP_DCU },
-    { AR_D5_MISC,	"D5_MISC",	DUMP_DCU },
-    { AR_D6_MISC,	"D6_MISC",	DUMP_DCU },
-    { AR_D7_MISC,	"D7_MISC",	DUMP_DCU },
-    { AR_D8_MISC,	"D8_MISC",	DUMP_DCU },
-    { AR_D9_MISC,	"D9_MISC",	DUMP_DCU },
-
-    { AR_D_SEQNUM,	"D_SEQ",	DUMP_BASIC | DUMP_DCU },
-    { AR_D_GBL_IFS_SIFS,"D_SIFS",	DUMP_BASIC },
-    { AR_D_GBL_IFS_SLOT,"D_SLOT",	DUMP_BASIC },
-    { AR_D_GBL_IFS_EIFS,"D_EIFS",	DUMP_BASIC },
-    { AR_D_GBL_IFS_MISC,"D_MISC",	DUMP_BASIC },
-    { AR_D_FPCTL,	"D_FPCTL",	DUMP_BASIC },
-    { AR_D_TXPSE,	"D_TXPSE",	DUMP_BASIC },
-#if 0
-    { AR_D_TXBLK_CMD,	"D_CMD",	DUMP_BASIC },
-    { AR_D_TXBLK_DATA,	"D_DATA",	DUMP_BASIC },
-    { AR_D_TXBLK_CLR,	"D_CLR",	DUMP_BASIC },
-    { AR_D_TXBLK_SET,	"D_SET",	DUMP_BASIC },
-#endif
-    { AR_RC,		"RC",		DUMP_BASIC },
-    { AR_SCR,		"SCR",		DUMP_BASIC },
-    { AR_INTPEND,	"INTPEND",	DUMP_BASIC },
-    { AR_SFR,		"SFR",		DUMP_BASIC },
-    { AR_PCICFG,	"PCICFG",	DUMP_BASIC },
-    { AR_GPIOCR,	"GPIOCR",	DUMP_BASIC },
-    { AR_GPIODO,	"GPIODO",	DUMP_BASIC },
-    { AR_GPIODI,	"GPIODI",	DUMP_BASIC },
-    { AR_SREV,		"SREV",		DUMP_BASIC },
-
-    { AR_PCIE_PMC,	"PCIEPMC",	DUMP_BASIC, SREV(4,8), SREV(13,7) },
-    { AR_PCIE_SERDES,	"SERDES",	DUMP_BASIC, SREV(4,8), SREV(13,7) },
-    { AR_PCIE_SERDES2,	"SERDES2",	DUMP_BASIC, SREV(4,8), SREV(13,7) },
+    DEFVOID(AR_ISR_RAC,		"ISR_RAC"),
+    DEFINT(AR_ISR_S0_S,		"ISR_S0_S"),
+    DEFINT(AR_ISR_S1_S,		"ISR_S1_S"),
+    DEFINT(AR_ISR_S2_S,		"ISR_S2_S"),
+    DEFINT(AR_ISR_S3_S,		"ISR_S3_S"),
+    DEFINT(AR_ISR_S4_S,		"ISR_S4_S"),
+
+    DEFBASIC(AR_DMADBG_0,	"DMADBG0"),
+    DEFBASIC(AR_DMADBG_1,	"DMADBG1"),
+    DEFBASIC(AR_DMADBG_2,	"DMADBG2"),
+    DEFBASIC(AR_DMADBG_3,	"DMADBG3"),
+    DEFBASIC(AR_DMADBG_4,	"DMADBG4"),
+    DEFBASIC(AR_DMADBG_5,	"DMADBG5"),
+    DEFBASIC(AR_DMADBG_6,	"DMADBG6"),
+    DEFBASIC(AR_DMADBG_7,	"DMADBG7"),
+
+    DEFBASIC(AR_DCM_A,		"DCM_A"),
+    DEFBASIC(AR_DCM_D,		"DCM_D"),
+    DEFBASIC(AR_DCCFG,		"DCCFG"),
+    DEFBASIC(AR_CCFG,		"CCFG"),
+    DEFBASIC(AR_CCUCFG,		"CCUCFG"),
+    DEFBASIC(AR_CPC_0,		"CPC0"),
+    DEFBASIC(AR_CPC_1,		"CPC1"),
+    DEFBASIC(AR_CPC_2,		"CPC2"),
+    DEFBASIC(AR_CPC_3,		"CPC3"),
+    DEFBASIC(AR_CPCOVF,		"CPCOVF"),
+
+    DEFQCU(AR_Q0_TXDP,		"Q0_TXDP"),
+    DEFQCU(AR_Q1_TXDP,		"Q1_TXDP"),
+    DEFQCU(AR_Q2_TXDP,		"Q2_TXDP"),
+    DEFQCU(AR_Q3_TXDP,		"Q3_TXDP"),
+    DEFQCU(AR_Q4_TXDP,		"Q4_TXDP"),
+    DEFQCU(AR_Q5_TXDP,		"Q5_TXDP"),
+    DEFQCU(AR_Q6_TXDP,		"Q6_TXDP"),
+    DEFQCU(AR_Q7_TXDP,		"Q7_TXDP"),
+    DEFQCU(AR_Q8_TXDP,		"Q8_TXDP"),
+    DEFQCU(AR_Q9_TXDP,		"Q9_TXDP"),
+
+    DEFQCU(AR_Q_TXE,		"Q_TXE"),
+    DEFQCU(AR_Q_TXD,		"Q_TXD"),
+
+    DEFQCU(AR_Q0_CBRCFG,	"Q0_CBR"),
+    DEFQCU(AR_Q1_CBRCFG,	"Q1_CBR"),
+    DEFQCU(AR_Q2_CBRCFG,	"Q2_CBR"),
+    DEFQCU(AR_Q3_CBRCFG,	"Q3_CBR"),
+    DEFQCU(AR_Q4_CBRCFG,	"Q4_CBR"),
+    DEFQCU(AR_Q5_CBRCFG,	"Q5_CBR"),
+    DEFQCU(AR_Q6_CBRCFG,	"Q6_CBR"),
+    DEFQCU(AR_Q7_CBRCFG,	"Q7_CBR"),
+    DEFQCU(AR_Q8_CBRCFG,	"Q8_CBR"),
+    DEFQCU(AR_Q9_CBRCFG,	"Q9_CBR"),
+
+    DEFQCU(AR_Q0_RDYTIMECFG,	"Q0_RDYT"),
+    DEFQCU(AR_Q1_RDYTIMECFG,	"Q1_RDYT"),
+    DEFQCU(AR_Q2_RDYTIMECFG,	"Q2_RDYT"),
+    DEFQCU(AR_Q3_RDYTIMECFG,	"Q3_RDYT"),
+    DEFQCU(AR_Q4_RDYTIMECFG,	"Q4_RDYT"),
+    DEFQCU(AR_Q5_RDYTIMECFG,	"Q5_RDYT"),
+    DEFQCU(AR_Q6_RDYTIMECFG,	"Q6_RDYT"),
+    DEFQCU(AR_Q7_RDYTIMECFG,	"Q7_RDYT"),
+    DEFQCU(AR_Q8_RDYTIMECFG,	"Q8_RDYT"),
+    DEFQCU(AR_Q9_RDYTIMECFG,	"Q9_RDYT"),
+
+    DEFQCU(AR_Q_ONESHOTARM_SC,	"Q_ONESHOTARM_SC"),
+    DEFQCU(AR_Q_ONESHOTARM_CC,	"Q_ONESHOTARM_CC"),
+
+    DEFQCU(AR_Q0_MISC,		"Q0_MISC"),
+    DEFQCU(AR_Q1_MISC,		"Q1_MISC"),

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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