Date: Thu, 29 Jul 2010 23:41:20 +0200 From: Alexander Fiveg <pebu3op@googlemail.com> To: Andriy Gapon <avg@icyb.net.ua> Cc: freebsd-hackers@freebsd.org, Sergey Babkin <babkin@verizon.net> Subject: Re: coherence-problem on the mapped memory buffer Message-ID: <201007292341.21123.pebu3op@googlemail.com> In-Reply-To: <4C51E198.8060800@icyb.net.ua> References: <382607918.1356296.1280433776963.JavaMail.root@vms170009.mailsrvcs.net> <4C51E198.8060800@icyb.net.ua>
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On Thursday 29 July 2010 22:16:24 Andriy Gapon wrote: > on 29/07/2010 23:02 Sergey Babkin said the following: > > Jul 29, 2010 12:58:07 PM, avg@icyb.net.ua wrote: > >> on 29/07/2010 19:13 Andriy Gapon said the following: > >>> on 29/07/2010 17:13 Alexander Fiveg said the following: > >> > >> In fact I have a suspicion that the problem might have to do with > >> multiple mappings of the shared pages, but far from sure... > >> Take a look at Intel=C2=AE 64 and IA-32 Architectures Software Develop= er=E2=80=99s > >> Manual Volume 3A - System Programming Guide, Part 1; Chapter 11.12.4 > >> Programming the PAT; starting at the following words: > >> =C2=ABThe PAT allows any memory type to be specified in the page table= s, and > >> therefore it is possible to have a single physical page mapped to two = or > >> more different linear addresses, each with different memory types. Int= el > >> does not support this practice...=C2=BB > > > > My guess would be that the memory type is not marked as DMA-capable. > > AFAIK the Intel CPUs do the hardware snooping on the physical addresses, > > so they have no coherency issues benween themselves. However if a DMA > > writer changes the memory, this I think does not get normally propagated > > to the front-side bus, and the CPUs would not see it. You may need to > > either explicitly flush the CPU cache before accessing these pages or > > mark them as non-cacheable. > > My guess was approximately the same - if one mapping is done in kernel for > DMA purposes, then the memory type is, most likely, set to uncached. But > the userland mapping of the same pages most likely marks the same pages > (via different virtual addresses) as cached. Depending on the hardware a= nd > on what mappings were used on a particular CPU (core) to access that > memory, there could be differences in interaction with DMA. Thanks a lot for your answers. But i am afraid i do not have enough=20 experience to solve these tasks. Could you please provide me with helpful=20 information how to:=20 =2D get access to the pages associated with a certain memory-buffer ?=20 I mean, I want to get the structures, that describe the page properties I=20 should change (for instance, in order to make the page non-cacheable). if you are aware of any good papers or examples in the system code, where=20 these topics are covered, I would appreciate it if you gave me the=20 references.=20 Alex
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