Date: Thu, 15 Mar 2018 22:51:10 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r331032 - stable/11/sys/dev/sdhci Message-ID: <201803152251.w2FMpAuS068740@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: marius Date: Thu Mar 15 22:51:10 2018 New Revision: 331032 URL: https://svnweb.freebsd.org/changeset/base/331032 Log: MFC: r327315 Add quirks for Intel Denverton eMMC 5.0 controllers. Modified: stable/11/sys/dev/sdhci/sdhci_pci.c Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/dev/sdhci/sdhci_pci.c ============================================================================== --- stable/11/sys/dev/sdhci/sdhci_pci.c Thu Mar 15 22:42:28 2018 (r331031) +++ stable/11/sys/dev/sdhci/sdhci_pci.c Thu Mar 15 22:51:10 2018 (r331032) @@ -120,6 +120,12 @@ static const struct sdhci_device { SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, + { 0x19db8086, 0xffff, "Intel Denverton eMMC 5.0 Controller", + SDHCI_QUIRK_INTEL_POWER_UP_RESET | + SDHCI_QUIRK_WAIT_WHILE_BUSY | + SDHCI_QUIRK_MMC_DDR52 | + SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | + SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | SDHCI_QUIRK_INTEL_POWER_UP_RESET |
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201803152251.w2FMpAuS068740>