Date: Thu, 5 Dec 2013 21:49:14 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r259010 - in head/sys: conf powerpc/fpu Message-ID: <201312052149.rB5LnEcT011811@svn.freebsd.org>
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Author: jhb Date: Thu Dec 5 21:49:14 2013 New Revision: 259010 URL: http://svnweb.freebsd.org/changeset/base/259010 Log: Fix debug printfs in FPU_EMU to compile on powerpc64 and enable it for powerpc64. This fixes the LINT64 kernel config. Approved by: nwhitehorn (the idea, not the actual patch) Modified: head/sys/conf/files.powerpc head/sys/powerpc/fpu/fpu_emu.c Modified: head/sys/conf/files.powerpc ============================================================================== --- head/sys/conf/files.powerpc Thu Dec 5 21:46:29 2013 (r259009) +++ head/sys/conf/files.powerpc Thu Dec 5 21:49:14 2013 (r259010) @@ -106,15 +106,15 @@ powerpc/booke/pmap.c optional booke powerpc/booke/trap.c optional booke powerpc/cpufreq/dfs.c optional cpufreq powerpc/cpufreq/pcr.c optional cpufreq aim -powerpc/fpu/fpu_add.c optional fpu_emu powerpc -powerpc/fpu/fpu_compare.c optional fpu_emu powerpc -powerpc/fpu/fpu_div.c optional fpu_emu powerpc -powerpc/fpu/fpu_emu.c optional fpu_emu powerpc -powerpc/fpu/fpu_explode.c optional fpu_emu powerpc -powerpc/fpu/fpu_implode.c optional fpu_emu powerpc -powerpc/fpu/fpu_mul.c optional fpu_emu powerpc -powerpc/fpu/fpu_sqrt.c optional fpu_emu powerpc -powerpc/fpu/fpu_subr.c optional fpu_emu powerpc +powerpc/fpu/fpu_add.c optional fpu_emu +powerpc/fpu/fpu_compare.c optional fpu_emu +powerpc/fpu/fpu_div.c optional fpu_emu +powerpc/fpu/fpu_emu.c optional fpu_emu +powerpc/fpu/fpu_explode.c optional fpu_emu +powerpc/fpu/fpu_implode.c optional fpu_emu +powerpc/fpu/fpu_mul.c optional fpu_emu +powerpc/fpu/fpu_sqrt.c optional fpu_emu +powerpc/fpu/fpu_subr.c optional fpu_emu powerpc/mambo/mambocall.S optional mambo powerpc/mambo/mambo.c optional mambo powerpc/mambo/mambo_console.c optional mambo Modified: head/sys/powerpc/fpu/fpu_emu.c ============================================================================== --- head/sys/powerpc/fpu/fpu_emu.c Thu Dec 5 21:46:29 2013 (r259009) +++ head/sys/powerpc/fpu/fpu_emu.c Thu Dec 5 21:49:14 2013 (r259010) @@ -326,8 +326,10 @@ fpu_execute(struct trapframe *tf, struct /* Store as integer */ ra = instr.i_x.i_ra; rb = instr.i_x.i_rb; - DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", - ra, tf->fixreg[ra], rb, tf->fixreg[rb])); + DPRINTF(FPE_INSN, + ("reg %d has %jx reg %d has %jx\n", + ra, (uintmax_t)tf->fixreg[ra], rb, + (uintmax_t)tf->fixreg[rb])); addr = tf->fixreg[rb]; if (ra != 0) @@ -356,8 +358,9 @@ fpu_execute(struct trapframe *tf, struct /* calculate EA of load/store */ ra = instr.i_x.i_ra; rb = instr.i_x.i_rb; - DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", - ra, tf->fixreg[ra], rb, tf->fixreg[rb])); + DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", + ra, (uintmax_t)tf->fixreg[ra], rb, + (uintmax_t)tf->fixreg[rb])); addr = tf->fixreg[rb]; if (ra != 0) addr += tf->fixreg[ra]; @@ -373,8 +376,9 @@ fpu_execute(struct trapframe *tf, struct /* calculate EA of load/store */ ra = instr.i_d.i_ra; addr = instr.i_d.i_d; - DPRINTF(FPE_INSN, ("reg %d has %x displ %x\n", - ra, tf->fixreg[ra], addr)); + DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", + ra, (uintmax_t)tf->fixreg[ra], + (uintmax_t)addr)); if (ra != 0) addr += tf->fixreg[ra]; rt = instr.i_d.i_rt; @@ -420,7 +424,7 @@ fpu_execute(struct trapframe *tf, struct return (0); #ifdef notyet } else if (instr.i_any.i_opcd == OPC_load_st_62) { - /* These are 64-bit extenstions */ + /* These are 64-bit extensions */ return (NOTFPU); #endif } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || @@ -784,7 +788,8 @@ fpu_execute(struct trapframe *tf, struct /* Move fpu condition codes to cr[1] */ tf->cr &= ~(0xf0000000>>bf); tf->cr |= (cond>>bf); - DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->cr, cond)); + DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", + bf/4, (uintmax_t)tf->cr, cond)); } ((int *)&fs->fpscr)[1] = fsr;
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