Date: Fri, 14 Nov 2008 00:48:48 -0800 (PST) From: Won De Erick <won.derick@yahoo.com> To: John Baldwin <jhb@freebsd.org>, freebsd-hardware@freebsd.org Cc: Jeremy Chadwick <koitsu@freebsd.org> Subject: Re: IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming HIGH CPU usage Message-ID: <829178.39837.qm@web45811.mail.sp1.yahoo.com> References: <704830.24415.qm@web45815.mail.sp1.yahoo.com> <366483.43588.qm@web45807.mail.sp1.yahoo.com> <20081113081936.GA14779@icarus.home.lan> <200811131438.25904.jhb@freebsd.org>
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> ----- Original Message ---- > From: John Baldwin <jhb@freebsd.org> > To: freebsd-hardware@freebsd.org > Cc: Jeremy Chadwick <koitsu@freebsd.org>; Won De Erick <won.derick@yahoo.com> > Sent: Friday, November 14, 2008 3:38:25 AM > Subject: Re: IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming HIGH CPU usage > > On Thursday 13 November 2008 03:19:36 am Jeremy Chadwick wrote: > > On Thu, Nov 13, 2008 at 12:07:37AM -0800, Won De Erick wrote: > > > Noted on this, I will update you through this thread. > > > > > > However is there any possibility of the following: > > > > > > > I don't know if there's a way to split the interrupt request for each bce's Rx and Tx, > > > > which means a total of four IRQs, and eventually four cores (or 4 CPUs) > > > > for the transactions. With this way, the IDLE processors would be utilized. > > > > > > What I mean here is, for the two interfaces: > > > > > > one IRQ for bce0 Rx > > > one IRQ for bce0 Tx > > > one IRQ for bce1 Rx > > > one IRQ for bce1 Tx > > > > I can't even begin to imagine how this would be possible on any NIC. > igb(4) does it. It is quite possible and one of the purposes of MSI. > However, the current bce(4) hardware does not support this. It only allows > for a single message and thus a single IRQ per-device. based from the man pages, igb driver supports Intel NICs w/ controllers starting from Intel NIC controller 82574. One Intel NIC (controller: 82576, see http://www.intel.com/Assets/PDF/prodbrief/320116.pdf) says it supports MSIX which minimizes the overhead of interrupts and allows load balancing of interrupt handling between multiple cores/CPUs. I should want a little more explanation how this feature being handled by MSIX. Thanks a lot. > -- > John Baldwin
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