Date: Mon, 9 Feb 2009 01:16:36 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/dev/re if_re.c src/sys/pci if_rlreg.h Message-ID: <200902090117.n191H7V6072207@repoman.freebsd.org>
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yongari 2009-02-09 01:16:36 UTC
FreeBSD src repository
Modified files: (Branch: RELENG_7)
sys/dev/re if_re.c
sys/pci if_rlreg.h
Log:
SVN rev 188356 on 2009-02-09 01:16:36Z by yongari
MFC: r185752-185753,185756,185896
r185752:
Make sure to return the result of meida change request.
Previously it used to return success regardless of the result.
r185753:
o Implemented miibus_statchg handler. It detects whether re(4)
established a valid link or not. In miibus_statchg handler add a
check for established link is valid one for the controller(e.g.
1000baseT is not a valid link for fastethernet controllers.)
o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers.
o Added additional check to know whether we've really encountered
watchdog timeouts or missed Tx completion interrupts. This change
may help to track down the cause of watchdog timeouts.
o In interrupt handler, removed a check for link state change
interrupt. Not all controllers have the bit and re(4) did not
rely on the event for a long time. In addition, re(4) didn't
request the interrupt in RL_IMR register.
r185756:
Reduce spin wait time consumed in GMII register access routines.
Waiting for 1ms for each GMII register access looks overkill and it
may also decrease overall performance of driver because re(4)
invokes mii_tick for every hz.
r185896:
Partly revert r185756. RTL8169SC doesn't like reduced delays in
GMII access while Tx/Rx is in progress.
Revision Changes Path
1.95.2.38 +54 -32 src/sys/dev/re/if_re.c
1.67.2.17 +1 -0 src/sys/pci/if_rlreg.h
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