Date: Thu, 10 Dec 2015 09:34:34 -0800 From: John Baldwin <jhb@freebsd.org> To: Andrew Turner <andrew@freebsd.org> Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r292064 - head/sys/arm64/arm64 Message-ID: <2223711.lepPF7yQe2@ralph.baldwin.cx> In-Reply-To: <201512101640.tBAGec5X072851@repo.freebsd.org> References: <201512101640.tBAGec5X072851@repo.freebsd.org>
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On Thursday, December 10, 2015 04:40:38 PM Andrew Turner wrote: > Author: andrew > Date: Thu Dec 10 16:40:38 2015 > New Revision: 292064 > URL: https://svnweb.freebsd.org/changeset/base/292064 > > Log: > Add support for the GICv2M extension to the GICv2 interrupt controller. > This is (oddly) specified in the ARM Server Base System Architecture. It > extends the GICv2 to support MSI and MSI-X interrupts, however only the > latter are currently supported. MSI and MSI-X only different in the config registers used to configure them in the PCI function. The on-wire format of the PCI transaction is identical, so from a PIC's perspective there should be no difference. They are all just MSI messages. This is why both MSI and MSI-X interrupt resources use the same PCIB_MAP_MSI() method to map a given IRQ to an (address, data) tuple. -- John Baldwin
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