Date: Sat, 10 Mar 2012 21:26:04 -0500 From: Patrick Kelsey <kelsey@ieee.org> To: freebsd-mips@freebsd.org Subject: [PATCH] MikroTik RB450G support Message-ID: <CAD44qMV=PEv3DFU7z1S=UhOYO3YMi7zqg7rsjn1zByTpN7ZxgA@mail.gmail.com>
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[-- Attachment #1 --]
Since I seem to be spending a lot of quality time with a MikroTik
RB450G lately, I thought it would be nice if someone could add support
for it to the tree :) Should any able and sympathetic souls be
reading this list, a ready .diff file covering what I have been using
is attached. This diff is mainly the work of Luiz Otavio O Souza,
massaged a bit for the current state of -HEAD. Note that the
RB450.hints file assumes the presence of the mmcspi driver in the
tree.
-Patrick
[-- Attachment #2 --]
Index: sys/mips/conf/RB4XX
===================================================================
--- sys/mips/conf/RB4XX (revision 0)
+++ sys/mips/conf/RB4XX (revision 0)
@@ -0,0 +1,132 @@
+#
+# $FreeBSD$
+#
+
+ident RB4XX
+makeoptions TARGET_BIG_ENDIAN
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+options HWPMC_HOOKS
+
+hints "RB450.hints"
+
+include "../atheros/std.ar71xx"
+
+#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE=""
+
+#options DDB
+#options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFSCLIENT #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+# options INVARIANTS
+# options INVARIANT_SUPPORT
+# options WITNESS
+# options WITNESS_SKIPSPIN
+# options DEBUG_REDZONE
+# options DEBUG_MEMGUARD
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+
+options MSDOSFS
+
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=arge1
+options BOOTP_COMPAT
+options ROOTDEVNAME=\"nfs:freebsd82dev64:/nfsroot/rb4xx\"
+
+device pci
+device ar71xx_pci
+
+# 802.11 framework
+# options IEEE80211_DEBUG
+# options IEEE80211_ALQ
+# options IEEE80211_SUPPORT_MESH
+# This option is currently broken for if_ath_tx.
+# options IEEE80211_SUPPORT_TDMA
+# options IEEE80211_AMPDU_AGE
+# device wlan # 802.11 support
+# device wlan_wep # 802.11 WEP support
+# device wlan_ccmp # 802.11 CCMP support
+# device wlan_tkip # 802.11 TKIP support
+# device wlan_xauth # 802.11 hostap support
+
+# Atheros wireless NICs
+# device ath # Atheros interface support
+# device ath_pci # Atheros PCI/Cardbus bus
+# options ATH_DEBUG
+# options ATH_DIAGAPI
+# options ATH_ENABLE_11N
+# options AH_DEBUG
+# options AH_DEBUG_ALQ
+# options ALQ
+# device ath_hal
+# option AH_SUPPORT_AR5416
+# device ath_rate_sample
+# option AH_RXCFG_SDMAMW_4BYTES
+# option AH_AR5416_INTERRUPT_MITIGATION
+# There's no DFS radar detection support yet so this won't actually
+# detect radars. It however does enable the rest of the channel change
+# machinery so DFS can be debugged.
+# option ATH_ENABLE_DFS
+
+device mii
+device arge
+
+# device usb
+# options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+# options USB_DEBUG
+# device ehci
+
+# device scbus
+# device umass
+# device da
+
+device spibus
+device ar71xx_spi
+device mmc
+device mmcsd
+device mmcspi
+device ar71xx_wdog
+
+device uart
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+# device gif # ip[46] in ip[46] tunneling protocol
+# device gre # generic encapsulation - only for IPv4 in IPv4 though atm
+
+# options ARGE_DEBUG # Enable if_arge debugging for now
+
+device gpio
+device gpioled
+
+#options RB_GPIO_PINS
+#options FIX_RB_MAC_ADDRESS
+
+options DUMMYNET
+options LIBALIAS
+options IPDIVERT
+options IPSTEALTH
+options IPFIREWALL
+options IPFIREWALL_NAT
+options IPFIREWALL_FORWARD
+options IPFIREWALL_VERBOSE
+options IPFIREWALL_DEFAULT_TO_ACCEPT
Index: sys/mips/conf/RB450.hints
===================================================================
--- sys/mips/conf/RB450.hints (revision 0)
+++ sys/mips/conf/RB450.hints (revision 0)
@@ -0,0 +1,70 @@
+#
+# $FreeBSD$
+#
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ohci
+#hint.ohci.0.at="apb0"
+#hint.ohci.0.maddr=0x1c000000
+#hint.ohci.0.msize=0x01000000
+#hint.ohci.0.irq=6
+
+#ehci
+#hint.ehci.0.at="nexus0"
+#hint.ehci.0.maddr=0x1b000000
+#hint.ehci.0.msize=0x01000000
+#hint.ehci.0.irq=1
+
+# pci
+#hint.pcib.0.at="nexus0"
+#hint.pcib.0.irq=0
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+# PHY0, PHY1, PHY2, PHY3
+hint.arge.0.phymask=0x0f
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1A000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+# PHY4
+hint.arge.1.phymask=0x10
+
+# SPI controller
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+# SPI microSD slot
+hint.mmcspi.0.at="spibus0"
+hint.mmcspi.0.cs=2
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# GPIO
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
+
+# User led
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="user"
+# pin 4
+hint.gpioled.0.pins=0x0010
+
+# hwpmc device
+hint.ar71xx_pmc.0.at="apb0"
+hint.ar71xx_pmc.0.irq=5
Index: sys/mips/atheros/ar71xx_machdep.c
===================================================================
--- sys/mips/atheros/ar71xx_machdep.c (revision 231894)
+++ sys/mips/atheros/ar71xx_machdep.c (working copy)
@@ -64,6 +64,7 @@
/* 4KB static data aread to keep a copy of the bootload env until
the dynamic kenv is setup */
char boot1_env[4096];
+char board_model[64];
/*
* We get a string in from Redboot with the all the arguments together,
@@ -168,7 +169,7 @@
__register_t a2 __unused, __register_t a3 __unused)
{
uint64_t platform_counter_freq;
- int argc = 0, i;
+ int argc = 0, i, board_mem, count = 0;
char **argv = NULL, **envp = NULL;
vm_offset_t kernend;
@@ -197,6 +198,27 @@
}
}
+ /* Parse cmd arguments */
+ if (MIPS_IS_VALID_PTR(argv)) {
+ for (i = 0; i < argc; i++) {
+ if (strncmp(argv[i], "kmac=", 5) == 0) {
+ count = sscanf(argv[i] + 5, "%x:%x:%x:%x:%x:%x",
+ &ar711_base_mac[0], &ar711_base_mac[1],
+ &ar711_base_mac[2], &ar711_base_mac[3],
+ &ar711_base_mac[4], &ar711_base_mac[5]);
+ if (count < 6)
+ memset(ar711_base_mac, 0,
+ sizeof(ar711_base_mac));
+ } else if (strncmp(argv[i], "mem=", 4) == 0) {
+ if (sscanf(argv[i] + 4, "%dM", &board_mem) == 1)
+ realmem = btoc(board_mem * 1024 * 1024);
+ } else if (strncmp(argv[i], "board=", 6) == 0) {
+ strlcpy(board_model, argv[i] + 6,
+ sizeof(board_model));
+ }
+ }
+ }
+
/*
* Just wild guess. RedBoot let us down and didn't reported
* memory size
Index: sys/mips/atheros/if_arge.c
===================================================================
--- sys/mips/atheros/if_arge.c (revision 231894)
+++ sys/mips/atheros/if_arge.c (working copy)
@@ -180,6 +180,8 @@
*/
extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
+extern char board_model[64];
+
static struct mtx miibus_mtx;
MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
@@ -395,8 +397,15 @@
eaddr[5] = (rnd >> 8) & 0xff;
}
- if (sc->arge_mac_unit != 0)
- eaddr[5] += sc->arge_mac_unit;
+ if (strncmp(board_model, "450", 3) == 0 ||
+ strncmp(board_model, "433", 3) == 0 ||
+ strncmp(board_model, "493", 3) == 0) {
+ if (sc->arge_mac_unit == 0)
+ eaddr[5] += 1;
+ } else {
+ if (sc->arge_mac_unit != 0)
+ eaddr[5] += sc->arge_mac_unit;
+ }
if (arge_dma_alloc(sc) != 0) {
error = ENXIO;
Index: sys/mips/atheros/ar71xx_chip.c
===================================================================
--- sys/mips/atheros/ar71xx_chip.c (revision 232725)
+++ sys/mips/atheros/ar71xx_chip.c (working copy)
@@ -136,21 +136,35 @@
return ((reg & mask) == mask);
}
+static __inline void
+ar71xx_chip_set_mii_speed(uint32_t reg, uint32_t ctrl)
+{
+ uint32_t val;
+
+ val = ATH_READ_REG(reg);
+ val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+ val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
+ ATH_WRITE_REG(reg, val);
+}
+
/* Speed is either 10, 100 or 1000 */
static void
ar71xx_chip_set_pll_ge(int unit, int speed)
{
- uint32_t pll;
+ uint32_t ctrl, pll;
switch (speed) {
case 10:
pll = PLL_ETH_INT_CLK_10;
+ ctrl = MII_CTRL_SPEED_10;
break;
case 100:
pll = PLL_ETH_INT_CLK_100;
+ ctrl = MII_CTRL_SPEED_100;
break;
case 1000:
pll = PLL_ETH_INT_CLK_1000;
+ ctrl = MII_CTRL_SPEED_1000;
break;
default:
printf("%s%d: invalid speed %d\n",
@@ -162,11 +176,13 @@
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT0_CLK, pll,
AR71XX_PLL_ETH0_SHIFT);
+ ar71xx_chip_set_mii_speed(AR71XX_MII0_CTRL, ctrl);
break;
case 1:
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT1_CLK, pll,
AR71XX_PLL_ETH1_SHIFT);
+ ar71xx_chip_set_mii_speed(AR71XX_MII1_CTRL, ctrl);
break;
default:
printf("%s: invalid PLL set for arge unit: %d\n",
Index: sys/mips/atheros/ar71xxreg.h
===================================================================
--- sys/mips/atheros/ar71xxreg.h (revision 231894)
+++ sys/mips/atheros/ar71xxreg.h (working copy)
@@ -270,6 +270,13 @@
/*
* GigE adapters region
*/
+#define AR71XX_MII0_CTRL 0x18070000
+#define AR71XX_MII1_CTRL 0x18070004
+#define MII_CTRL_SPEED_SHIFT 4
+#define MII_CTRL_SPEED_MASK 3
+#define MII_CTRL_SPEED_10 0
+#define MII_CTRL_SPEED_100 1
+#define MII_CTRL_SPEED_1000 2
#define AR71XX_MAC0_BASE 0x19000000
#define AR71XX_MAC1_BASE 0x1A000000
/*
help
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