Date: Mon, 3 Dec 2001 14:14:54 -0800 (PST) From: Matthew Dillon <dillon@apollo.backplane.com> To: Søren Schmidt <sos@freebsd.dk> Cc: nuzrin@goose.net.my, Miklos Niedermayer <mico@bsd.hu>, Greg Lehey <grog@FreeBSD.ORG>, current@FreeBSD.ORG Subject: Re: HEADSUP ATA support for newer SiS chipsets added Message-ID: <200112032214.fB3MEst98950@apollo.backplane.com> References: <200112031058.fB3AwDT04544@freebsd.dk>
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:Hmm, I've just played around a bit, it seems we are hit by interrupt
:latency or something, if you limit the transfer to 128k, which allows
:the ATA controller to fetch it in one go, you will see the expected
:transfer rates. Now I dont see this on PCI based controllers, and that
:hints that the problem could be the fact that the two onboard controllers
:sits on irq 14 & 15 making them the lowest priority devices in the system,
:and that could cause the interrupt latency I'm seeing which then again
:causes the bad transfer rates on transfers that need to transfer more
:that one transaction full of data (ie max 128k).
:
:-Søren
The larger transfers are probably choking the IDE drive's pipelining
capabilities. That's my guess, anyway. I avoid IDE like the plague.
-Matt
Matthew Dillon
<dillon@backplane.com>
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