Date: Sat, 28 Feb 2015 00:17:30 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279387 - in head/sys/mips/nlm: . hal Message-ID: <201502280017.t1S0HURe096457@svn.freebsd.org>
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Author: jchandra Date: Sat Feb 28 00:17:29 2015 New Revision: 279387 URL: https://svnweb.freebsd.org/changeset/base/279387 Log: Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit. Modified: head/sys/mips/nlm/board.c head/sys/mips/nlm/board.h head/sys/mips/nlm/board_cpld.c head/sys/mips/nlm/board_eeprom.c head/sys/mips/nlm/bus_space_rmi_pci.c head/sys/mips/nlm/cms.c head/sys/mips/nlm/hal/fmn.h head/sys/mips/nlm/hal/gbu.h head/sys/mips/nlm/hal/interlaken.h head/sys/mips/nlm/hal/mdio.h head/sys/mips/nlm/hal/mips-extns.h head/sys/mips/nlm/hal/mmu.h head/sys/mips/nlm/hal/nae.h head/sys/mips/nlm/hal/nlm_hal.c head/sys/mips/nlm/hal/nlmsaelib.h head/sys/mips/nlm/hal/pcibus.h head/sys/mips/nlm/hal/poe.h head/sys/mips/nlm/hal/sgmii.h head/sys/mips/nlm/hal/ucore_loader.h head/sys/mips/nlm/hal/usb.h head/sys/mips/nlm/hal/xaui.h head/sys/mips/nlm/interrupt.h head/sys/mips/nlm/intr_machdep.c head/sys/mips/nlm/mpreset.S head/sys/mips/nlm/msgring.h head/sys/mips/nlm/tick.c head/sys/mips/nlm/uart_cpu_xlp.c head/sys/mips/nlm/usb_init.c head/sys/mips/nlm/xlp.h head/sys/mips/nlm/xlp_machdep.c head/sys/mips/nlm/xlp_pci.c Modified: head/sys/mips/nlm/board.c ============================================================================== --- head/sys/mips/nlm/board.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/board.c Sat Feb 28 00:17:29 2015 (r279387) @@ -71,7 +71,7 @@ static struct vfbid_tbl nlm_vfbid[] = { {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008}, {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004}, {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000}, - /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ + /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ {31, 127}, {30, 123}, {29, 119}, {28, 115}, {27, 111}, {26, 107}, {25, 103}, {24, 99}, {23, 95}, {22, 91}, {21, 87}, {20, 83}, @@ -87,7 +87,7 @@ static struct vfbid_tbl nlm3xx_vfbid[] = {127, 0}, /* NAE <-> NAE mappings */ {39, 503}, {38, 502}, {37, 501}, {36, 500}, {35, 499}, {34, 498}, {33, 497}, {32, 496}, - /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ + /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ {31, 127}, {30, 123}, {29, 119}, {28, 115}, {27, 111}, {26, 107}, {25, 103}, {24, 99}, {23, 95}, {22, 91}, {21, 87}, {20, 83}, @@ -240,7 +240,7 @@ nlm_setup_port_defaults(struct xlp_port_ /* XLP 8XX evaluation boards have the following phy-addr * assignment. There are two external mdio buses in XLP -- * bus 0 and bus 1. The management ports (16 and 17) are - * on mdio bus 0 while blocks/complexes[0 to 3] are all + * on mdio bus 0 while blocks/complexes[0 to 3] are all * on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16 * and 17) match the port numbers. * These are the details: @@ -263,7 +263,7 @@ nlm_setup_port_defaults(struct xlp_port_ * 3 2 14 1 * 3 3 13 1 * - * 4 0 16 0 + * 4 0 16 0 * 4 1 17 0 * * The XLP 3XX evaluation boards have the following phy-addr @@ -366,7 +366,7 @@ nlm_print_processor_info(void) } /* - * All our knowledge of chip and board that cannot be detected by probing + * All our knowledge of chip and board that cannot be detected by probing * at run-time goes here */ static int Modified: head/sys/mips/nlm/board.h ============================================================================== --- head/sys/mips/nlm/board.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/board.h Sat Feb 28 00:17:29 2015 (r279387) @@ -5,7 +5,7 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: - * + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -40,7 +40,7 @@ */ #define EEPROM_I2CBUS 1 #define EEPROM_I2CADDR 0xAE -#define EEPROM_SIZE 48 +#define EEPROM_SIZE 48 #define EEPROM_MACADDR_OFFSET 2 /* used if there is no FDT */ @@ -113,7 +113,7 @@ struct xlp_block_ivars { }; struct xlp_nae_ivars { - int node; + int node; int nblocks; u_int blockmask; u_int ilmask; Modified: head/sys/mips/nlm/board_cpld.c ============================================================================== --- head/sys/mips/nlm/board_cpld.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/board_cpld.c Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Modified: head/sys/mips/nlm/board_eeprom.c ============================================================================== --- head/sys/mips/nlm/board_eeprom.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/board_eeprom.c Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -78,7 +78,7 @@ oc_rd_cmd(uint8_t cmd) data = oc_read_reg(OC_I2C_DATA_REG); return (data); } - + static int oc_wr_cmd(uint8_t data, uint8_t cmd) { @@ -142,7 +142,7 @@ nlm_board_eeprom_read(int node, int bus, err = "No ack after read start"; goto err_exit_stop; } - + for (i = 0; i < sz - 1; i++) { if ((rd = oc_rd_cmd(OC_COMMAND_READ)) < 0) { err = "I2C read data byte failed."; Modified: head/sys/mips/nlm/bus_space_rmi_pci.c ============================================================================== --- head/sys/mips/nlm/bus_space_rmi_pci.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/bus_space_rmi_pci.c Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS @@ -46,199 +46,202 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/cache.h> -static int +static int rmi_pci_bus_space_map(void *t, bus_addr_t addr, bus_size_t size, int flags, bus_space_handle_t * bshp); -static void +static void rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, bus_size_t size); -static int +static int rmi_pci_bus_space_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t * nbshp); -static u_int8_t +static u_int8_t rmi_pci_bus_space_read_1(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int16_t +static u_int16_t rmi_pci_bus_space_read_2(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int32_t +static u_int32_t rmi_pci_bus_space_read_4(void *t, bus_space_handle_t handle, bus_size_t offset); -static void +static void rmi_pci_bus_space_read_multi_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t value); -static void +static void rmi_pci_bus_space_write_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t value); -static void +static void rmi_pci_bus_space_write_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t value); -static void +static void rmi_pci_bus_space_write_multi_1(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_2(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_4(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int32_t * addr, size_t count); - -static void +static void rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t value, size_t count); -static void + +static void rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t value, size_t count); -static void +static void rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, bus_size_t offset __unused, bus_size_t len __unused, int flags); -static void +static void rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, size_t count); -u_int8_t +u_int8_t rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int16_t +static u_int16_t rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int32_t +static u_int32_t rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset); -static void + +static void rmi_pci_bus_space_read_multi_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count); -void +void rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t value); -static void + +static void rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t value); -static void +static void rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t value); -static void +static void rmi_pci_bus_space_write_multi_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count); -static void + +static void rmi_pci_bus_space_write_multi_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, Modified: head/sys/mips/nlm/cms.c ============================================================================== --- head/sys/mips/nlm/cms.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/cms.c Sat Feb 28 00:17:29 2015 (r279387) @@ -107,7 +107,7 @@ static int fmn_loops[XLP_MAX_CORES * XLP static int polled = 0; /* We do only i/o device credit setup here. CPU credit setup is now - * moved to xlp_msgring_cpu_init() so that the credits get setup + * moved to xlp_msgring_cpu_init() so that the credits get setup * only if the CPU exists. xlp_msgring_cpu_init() gets called from * platform_init_ap; and this makes it easy for us to setup CMS * credits for various types of XLP chips, with varying number of @@ -198,9 +198,9 @@ xlp_handle_msg_vc(u_int vcmask, int max_ mflags = nlm_save_flags_cop2(); status = nlm_fmn_msgrcv(vc, &srcid, &size, &code, - &msg); + &msg); nlm_restore_flags(mflags); - if (status != 0) /* no msg or error */ + if (status != 0) /* no msg or error */ continue; if (srcid < 0 && srcid >= 1024) { printf("[%s]: bad src id %d\n", __func__, Modified: head/sys/mips/nlm/hal/fmn.h ============================================================================== --- head/sys/mips/nlm/hal/fmn.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/fmn.h Sat Feb 28 00:17:29 2015 (r279387) @@ -94,7 +94,7 @@ /* Each XLP chip can hold upto 32K messages on the chip itself */ #define CMS_ON_CHIP_MESG_SPACE (32*1024) #define CMS_MAX_ONCHIP_SEGMENTS 1024 -#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 +#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 /* FMN Network error */ #define CMS_ILLEGAL_DST_ERROR 0x100 Modified: head/sys/mips/nlm/hal/gbu.h ============================================================================== --- head/sys/mips/nlm/hal/gbu.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/gbu.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Modified: head/sys/mips/nlm/hal/interlaken.h ============================================================================== --- head/sys/mips/nlm/hal/interlaken.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/interlaken.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Modified: head/sys/mips/nlm/hal/mdio.h ============================================================================== --- head/sys/mips/nlm/hal/mdio.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/mdio.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -34,7 +34,7 @@ /** * @file_name mdio.h * @author Netlogic Microsystems -* @brief Access functions for XLP MDIO +* @brief Access functions for XLP MDIO */ #define INT_MDIO_CTRL 0x19 #define INT_MDIO_CTRL_DATA 0x1A Modified: head/sys/mips/nlm/hal/mips-extns.h ============================================================================== --- head/sys/mips/nlm/hal/mips-extns.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/mips-extns.h Sat Feb 28 00:17:29 2015 (r279387) @@ -161,7 +161,7 @@ nlm_ldaddwu(unsigned int value, unsigned #else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ /* - * 32 bit compilation, 64 bit values has to split + * 32 bit compilation, 64 bit values has to split */ #define read_c0_register64(reg, sel) \ ({ \ @@ -207,7 +207,7 @@ do { \ * cp0 register 9 sel 7 * bits 0...7 are same as status register 8...15 */ -static __inline uint64_t +static __inline uint64_t nlm_read_c0_eirr(void) { @@ -221,7 +221,7 @@ nlm_write_c0_eirr(uint64_t val) write_c0_register64(9, 6, val); } -static __inline uint64_t +static __inline uint64_t nlm_read_c0_eimr(void) { Modified: head/sys/mips/nlm/hal/mmu.h ============================================================================== --- head/sys/mips/nlm/hal/mmu.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/mmu.h Sat Feb 28 00:17:29 2015 (r279387) @@ -43,7 +43,7 @@ nlm_read_c0_config6(void) ".set push\n" ".set mips64\n" "mfc0 %0, $16, 6\n" - ".set pop\n" + ".set pop\n" : "=r" (rv)); return rv; @@ -56,7 +56,7 @@ nlm_write_c0_config6(uint32_t value) ".set push\n" ".set mips64\n" "mtc0 %0, $16, 6\n" - ".set pop\n" + ".set pop\n" : : "r" (value)); } @@ -69,7 +69,7 @@ nlm_read_c0_config7(void) ".set push\n" ".set mips64\n" "mfc0 %0, $16, 7\n" - ".set pop\n" + ".set pop\n" : "=r" (rv)); return rv; @@ -82,7 +82,7 @@ nlm_write_c0_config7(uint32_t value) ".set push\n" ".set mips64\n" "mtc0 %0, $16, 7\n" - ".set pop\n" + ".set pop\n" : : "r" (value)); } /** Modified: head/sys/mips/nlm/hal/nae.h ============================================================================== --- head/sys/mips/nlm/hal/nae.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/nae.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -457,7 +457,7 @@ #define XLP8XX_MS_FIFO_SZ 2048 #define XLP8XX_PKT_FIFO_SZ 16384 #define XLP8XX_PKTLEN_FIFO_SZ 2048 - + #define XLP8XX_MAX_STG2_OFFSET 0x7F #define XLP8XX_MAX_EH_OFFSET 0x7F #define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F Modified: head/sys/mips/nlm/hal/nlm_hal.c ============================================================================== --- head/sys/mips/nlm/hal/nlm_hal.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/nlm_hal.c Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS Modified: head/sys/mips/nlm/hal/nlmsaelib.h ============================================================================== --- head/sys/mips/nlm/hal/nlmsaelib.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/nlmsaelib.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -66,7 +66,7 @@ * Since buffer allocation for crypto at kernel is done as malloc, each * segment size is given as page size which is 4K by default */ -#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE +#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE #define MAX_KEY_LEN_IN_DW 20 @@ -83,16 +83,16 @@ enum nlm_cipher_algo { NLM_CIPHER_BYPASS = 0, NLM_CIPHER_DES = 1, - NLM_CIPHER_3DES = 2, + NLM_CIPHER_3DES = 2, NLM_CIPHER_AES128 = 3, NLM_CIPHER_AES192 = 4, - NLM_CIPHER_AES256 = 5, - NLM_CIPHER_ARC4 = 6, + NLM_CIPHER_AES256 = 5, + NLM_CIPHER_ARC4 = 6, NLM_CIPHER_KASUMI_F8 = 7, - NLM_CIPHER_SNOW3G_F8 = 8, - NLM_CIPHER_CAMELLIA128 = 9, - NLM_CIPHER_CAMELLIA192 = 0xA, - NLM_CIPHER_CAMELLIA256 = 0xB, + NLM_CIPHER_SNOW3G_F8 = 8, + NLM_CIPHER_CAMELLIA128 = 9, + NLM_CIPHER_CAMELLIA192 = 0xA, + NLM_CIPHER_CAMELLIA256 = 0xB, NLM_CIPHER_MAX = 0xC, }; @@ -153,7 +153,7 @@ enum nlm_hash_mode { NLM_HASH_MODE_CCM = 8, /* AES */ NLM_HASH_MODE_GCM = 9, /* AES */ NLM_HASH_MODE_MAX = 0xA, -}; +}; /** * @brief crypto control descriptor, should be cache aligned @@ -163,28 +163,28 @@ struct nlm_crypto_pkt_ctrl { uint64_t desc0; /* combination of cipher and hash keys */ uint64_t key[MAX_KEY_LEN_IN_DW]; - uint32_t cipherkeylen; - uint32_t hashkeylen; + uint32_t cipherkeylen; + uint32_t hashkeylen; uint32_t taglen; }; /** -* @brief crypto packet descriptor, should be cache aligned +* @brief crypto packet descriptor, should be cache aligned * @ingroup crypto */ struct nlm_crypto_pkt_param { uint64_t desc0; - uint64_t desc1; + uint64_t desc1; uint64_t desc2; uint64_t desc3; uint64_t segment[1][2]; }; static __inline__ uint64_t -nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type, +nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type, unsigned int func, uint64_t srcaddr) { - return (left_shift64(l3alloc, 61, 1) | + return (left_shift64(l3alloc, 61, 1) | left_shift64(type, 46, 7) | left_shift64(func, 40, 6) | left_shift64(srcaddr, 0, 40)); @@ -203,14 +203,14 @@ nlm_crypto_form_rsa_ecc_fmn_entry1(unsig /** * @brief Generate cypto control descriptor * @ingroup crypto -* hmac : 1 for hash with hmac +* hmac : 1 for hash with hmac * hashalg, see hash_alg enums * hashmode, see hash_mode enums * cipherhalg, see cipher_alg enums * ciphermode, see cipher_mode enums -* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32 -* arc4_keyinit : -* cfbmask : cipher text for feedback, +* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32 +* arc4_keyinit : +* cfbmask : cipher text for feedback, * 0(1 bit), 1(2 bits), 2(4 bits), 3(8 bits), 4(16bits), 5(32 bits), * 6(64 bits), 7(128 bits) */ @@ -220,13 +220,13 @@ nlm_crypto_form_pkt_ctrl_desc(unsigned i unsigned int arc4_cipherkeylen, unsigned int arc4_keyinit, unsigned int cfbmask) { - return (left_shift64(hmac, 61, 1) | - left_shift64(hashalg, 52, 8) | - left_shift64(hashmode, 43, 8) | - left_shift64(cipheralg, 34, 8) | - left_shift64(ciphermode, 25, 8) | - left_shift64(arc4_cipherkeylen, 18, 5) | - left_shift64(arc4_keyinit, 17, 1) | + return (left_shift64(hmac, 61, 1) | + left_shift64(hashalg, 52, 8) | + left_shift64(hashmode, 43, 8) | + left_shift64(cipheralg, 34, 8) | + left_shift64(ciphermode, 25, 8) | + left_shift64(arc4_cipherkeylen, 18, 5) | + left_shift64(arc4_keyinit, 17, 1) | left_shift64(cfbmask, 0, 3)); } /** @@ -264,7 +264,7 @@ nlm_crypto_form_pkt_desc1(unsigned int c { return (left_shift64_mask((cipherlen - 1), 32, 32) | left_shift64_mask((hashlen - 1), 0, 32)); -} +} /** * @brief Generate cypto packet descriptor 2 @@ -300,7 +300,7 @@ nlm_crypto_form_pkt_desc2(unsigned int i * taglen : length in bits of the tag generated by the auth engine * md5 (128 bits), sha1 (160), sha224 (224), sha384 (384), * sha512 (512), Kasumi (32), snow3g (32), gcm (128) -* hmacpad : 1 if hmac padding is already done +* hmacpad : 1 if hmac padding is already done */ static __inline__ uint64_t nlm_crypto_form_pkt_desc3(unsigned int designer_vc, unsigned int taglen, @@ -398,23 +398,23 @@ nlm_crypto_get_hklen_taglen(enum nlm_has *hklen = 64; } else if (hashalg == NLM_HASH_SHA) { switch (hashmode) { - case NLM_HASH_MODE_SHA1: + case NLM_HASH_MODE_SHA1: *taglen = 160; *hklen = 64; break; - case NLM_HASH_MODE_SHA224: + case NLM_HASH_MODE_SHA224: *taglen = 224; *hklen = 64; break; - case NLM_HASH_MODE_SHA256: + case NLM_HASH_MODE_SHA256: *taglen = 256; *hklen = 64; break; - case NLM_HASH_MODE_SHA384: + case NLM_HASH_MODE_SHA384: *taglen = 384; *hklen = 128; break; - case NLM_HASH_MODE_SHA512: + case NLM_HASH_MODE_SHA512: *taglen = 512; *hklen = 128; break; @@ -449,7 +449,7 @@ nlm_crypto_get_hklen_taglen(enum nlm_has /** * @brief Generate fill cryto control info structure * @ingroup crypto -* hmac : 1 for hash with hmac +* hmac : 1 for hash with hmac * hashalg: see above, hash_alg enums * hashmode: see above, hash_mode enums * cipherhalg: see above, cipher_alg enums @@ -465,7 +465,7 @@ nlm_crypto_fill_pkt_ctrl(struct nlm_cryp { unsigned int taglen = 0, hklen = 0; - ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode, + ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode, cipheralg, ciphermode, 0, 0, 0); memset(ctrl->key, 0, sizeof(ctrl->key)); if (cipherkey) @@ -480,7 +480,7 @@ nlm_crypto_fill_pkt_ctrl(struct nlm_cryp ctrl->cipherkeylen = cipherkeylen; ctrl->hashkeylen = hklen; ctrl->taglen = taglen; - + /* TODO : add the invalid checks and return error */ return (0); } @@ -529,8 +529,6 @@ nlm_crypto_fill_cipher_auth_pkt_param(st * cipheroff : cipher offset from start of data * cipherlen : cipher length in bytes */ - - static __inline__ void nlm_crypto_fill_cipher_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl, struct nlm_crypto_pkt_param *param, unsigned int encrypt, @@ -586,7 +584,7 @@ nlm_crypto_fill_src_seg(struct nlm_crypt } static __inline__ unsigned int -nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param, +nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param, int seg, unsigned char *output, unsigned int outlen) { unsigned off = 0, len = 0; Modified: head/sys/mips/nlm/hal/pcibus.h ============================================================================== --- head/sys/mips/nlm/hal/pcibus.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/pcibus.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS Modified: head/sys/mips/nlm/hal/poe.h ============================================================================== --- head/sys/mips/nlm/hal/poe.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/poe.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -277,7 +277,7 @@ nlm_poe_max_flows(uint64_t poe_pcibase) * thr_vcmask: destination VCs for a thread */ static __inline void -nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, +nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, uint32_t thr_vcmask, uint32_t *distvec) { uint32_t cpumask = 0, val; Modified: head/sys/mips/nlm/hal/sgmii.h ============================================================================== --- head/sys/mips/nlm/hal/sgmii.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/sgmii.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Modified: head/sys/mips/nlm/hal/ucore_loader.h ============================================================================== --- head/sys/mips/nlm/hal/ucore_loader.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/ucore_loader.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -52,7 +52,7 @@ nlm_ucore_load_image(uint64_t nae_base, nlm_store_word_daddr(addr, htobe32(p[i])); /* add a 'nop' if number of instructions are odd */ - if (size & 0x1) + if (size & 0x1) nlm_store_word_daddr(addr, 0x0); } @@ -66,11 +66,11 @@ nlm_ucore_write_sharedmem(uint64_t nae_b return (-1); ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); - /* set iram to zero */ + /* set iram to zero */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, (ucore_cfg & ~(0x1 << 7))); - nlm_store_word_daddr(addr + (index * 4), data); + nlm_store_word_daddr(addr + (index * 4), data); /* restore ucore config */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); @@ -84,11 +84,11 @@ nlm_ucore_read_sharedmem(uint64_t nae_ba uint32_t ucore_cfg, val; ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); - /* set iram to zero */ + /* set iram to zero */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, (ucore_cfg & ~(0x1 << 7))); - val = nlm_load_word_daddr(addr + (index * 4)); + val = nlm_load_word_daddr(addr + (index * 4)); /* restore ucore config */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); Modified: head/sys/mips/nlm/hal/usb.h ============================================================================== --- head/sys/mips/nlm/hal/usb.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/usb.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS Modified: head/sys/mips/nlm/hal/xaui.h ============================================================================== --- head/sys/mips/nlm/hal/xaui.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/hal/xaui.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,7 +12,7 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Modified: head/sys/mips/nlm/interrupt.h ============================================================================== --- head/sys/mips/nlm/interrupt.h Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/interrupt.h Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS Modified: head/sys/mips/nlm/intr_machdep.c ============================================================================== --- head/sys/mips/nlm/intr_machdep.c Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/intr_machdep.c Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS @@ -64,7 +64,7 @@ struct xlp_intrsrc { int irq; int irt; }; - + static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR]; static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR]; static int intrcnt_index; @@ -124,7 +124,7 @@ static void xlp_post_filter(void *source) { struct xlp_intrsrc *src = source; - + if (src->bus_ack) src->bus_ack(src->irq, src->bus_ack_arg); nlm_pic_ack(xlp_pic_base, src->irt); @@ -228,8 +228,8 @@ cpu_intr(struct trapframe *tf) eirr = nlm_read_c0_eirr(); eimr = nlm_read_c0_eimr(); eirr &= eimr; - - if (eirr == 0) { + + if (eirr == 0) { critical_exit(); return; } @@ -242,7 +242,7 @@ cpu_intr(struct trapframe *tf) critical_exit(); return; } - + /* FIXME sched pin >? LOCK>? */ for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) { if ((eirr & (1ULL << i)) == 0) @@ -295,7 +295,7 @@ cpu_init_interrupts() /* * Initialize all available vectors so spare IRQ - * would show up in systat output + * would show up in systat output */ for (i = 0; i < XLR_MAX_INTR; i++) { snprintf(name, MAXCOMLEN + 1, "int%d:", i); Modified: head/sys/mips/nlm/mpreset.S ============================================================================== --- head/sys/mips/nlm/mpreset.S Sat Feb 28 00:16:36 2015 (r279386) +++ head/sys/mips/nlm/mpreset.S Sat Feb 28 00:17:29 2015 (r279387) @@ -12,11 +12,11 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS @@ -124,7 +124,7 @@ nmi_handler: /* * Enable other threads in the core, called from thread 0 * of the core - */ + */ LEAF(xlp_enable_threads) /* * Save and restore callee saved registers of all ABIs @@ -152,7 +152,7 @@ LEAF(xlp_enable_threads) /* Use register number to work in o32 and n32 */ *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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