Date: Sat, 11 Oct 2008 11:39:05 GMT From: Patrick Lamaiziere <patpr@davenulle.org> To: freebsd-gnats-submit@FreeBSD.org Subject: kern/128014: AMD Geode CS5536 watchdog(9) not disabled Message-ID: <200810111139.m9BBd5Sc085300@www.freebsd.org> Resent-Message-ID: <200810111140.m9BBe0u8010755@freefall.freebsd.org>
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>Number: 128014
>Category: kern
>Synopsis: AMD Geode CS5536 watchdog(9) not disabled
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: sw-bug
>Submitter-Id: current-users
>Arrival-Date: Sat Oct 11 11:40:00 UTC 2008
>Closed-Date:
>Last-Modified:
>Originator: Patrick Lamaiziere
>Release: 8.0-CURRENT/i386
>Organization:
>Environment:
FreeBSD malpractice.lamaiziere.net 8.0-CURRENT FreeBSD 8.0-CURRENT #2: Fri Oct 10 11:19:40 CEST 2008 patrick@malpractice.lamaiziere.net:/usr/obj/usr/src/sys/NET5501 i386
>Description:
On the AMD Geode companion chipset CS5536 (by instance on a Soekris Net5501), the hardware watchdog is implemented by a MFGPT timer. When the timer has elapsed, the chipset does a hardware reset.
When the watchdog is disabled, the actual code (sys/i386/i386/geode.c) does not stop the timer, only the the hardware reset is disabled. So if the watchdog is enabled again after the timer has been elapsed, the chipset does a reset and the box reboots immediatly.
>How-To-Repeat:
watchdog -t 16; watchdog -t 0
(wait a bit)
watchdog -t 16 => hardware reset
>Fix:
The attached patch stops and resets the timer when the watchdog is disabled and never disables the hardware reset - if the timer has elapsed it's too late -
Patch attached with submission follows:
--- geode.c 2008-10-09 20:52:47.000000000 +0200
+++ /usr/src/sys/i386/i386/geode.c 2008-10-10 10:25:47.000000000 +0200
@@ -208,14 +208,11 @@
static void
cs5536_watchdog(void *foo __unused, u_int cmd, int *error)
{
- u_int u, p;
+ u_int u, p, s;
uint16_t a;
uint32_t m;
a = rdmsr(0x5140000d);
- m = rdmsr(0x51400029);
- m &= ~(1 << 24);
- wrmsr(0x51400029, m);
u = cmd & WD_INTERVAL;
if (u >= 30 && u <= 44) {
@@ -228,12 +225,24 @@
/* reset counter */
outw(a + 4, 0);
/* Arm reset mechanism */
+ m = rdmsr(0x51400029);
m |= (1 << 24);
wrmsr(0x51400029, m);
/* Start counter */
outw(a + 6, 0x8000);
*error = 0;
+ } else {
+ /*
+ * MFGPT_SETUP is write-once
+ * Check if the counter has been setup
+ */
+ s = inw(a + 6);
+ if (s & (1 << 12)) {
+ /* Stop and reset counter */
+ outw(a + 6, 0);
+ outw(a + 4, 0);
+ }
}
}
>Release-Note:
>Audit-Trail:
>Unformatted:
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