Date: Fri, 27 Sep 2024 03:41:40 GMT From: Kevin Bowling <kbowling@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: ea1afe5766c9 - stable/13 - ixgbe: use primary and block terminology Message-ID: <202409270341.48R3fePM055479@gitrepo.freebsd.org>
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The branch stable/13 has been updated by kbowling: URL: https://cgit.FreeBSD.org/src/commit/?id=ea1afe5766c97477c1ed010b1e1606ee8b5ddc9d commit ea1afe5766c97477c1ed010b1e1606ee8b5ddc9d Author: Marcin Jurczak <marcin.jurczak@intel.com> AuthorDate: 2024-09-20 03:18:00 +0000 Commit: Kevin Bowling <kbowling@FreeBSD.org> CommitDate: 2024-09-27 03:39:53 +0000 ixgbe: use primary and block terminology DPDK commit message net/ixgbe/base: replace non-inclusive language This patch removes non-inclusive language from code, user interface and comments. Signed-off-by: Marcin Jurczak <marcin.jurczak@intel.com> Reviewed-by: Alice Michael <alice.michael@intel.com> Obtained from: DPDK (f12a4bd) (cherry picked from commit 4530d49e68d331e9168d3a216d8a4b8e0d547578) --- sys/dev/ixgbe/ixgbe_common.c | 34 +++++++++++++++++----------------- sys/dev/ixgbe/ixgbe_common.h | 2 +- sys/dev/ixgbe/ixgbe_type.h | 10 +++++----- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/sys/dev/ixgbe/ixgbe_common.c b/sys/dev/ixgbe/ixgbe_common.c index ff422a01c741..7cf9b8d05127 100644 --- a/sys/dev/ixgbe/ixgbe_common.c +++ b/sys/dev/ixgbe/ixgbe_common.c @@ -171,7 +171,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) case ixgbe_media_type_fiber_fixed: case ixgbe_media_type_fiber_qsfp: case ixgbe_media_type_fiber: - /* flow control autoneg black list */ + /* flow control autoneg block list */ switch (hw->device_id) { case IXGBE_DEV_ID_X550EM_A_SFP: case IXGBE_DEV_ID_X550EM_A_SFP_N: @@ -1146,10 +1146,10 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) msec_delay(2); /* - * Prevent the PCI-E bus from hanging by disabling PCI-E master + * Prevent the PCI-E bus from hanging by disabling PCI-E primary * access and verify no pending requests */ - return ixgbe_disable_pcie_master(hw); + return ixgbe_disable_pcie_primary(hw); } /** @@ -3208,32 +3208,32 @@ static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) } /** - * ixgbe_disable_pcie_master - Disable PCI-express master access + * ixgbe_disable_pcie_primary - Disable PCI-express primary access * @hw: pointer to hardware structure * - * Disables PCI-Express master access and verifies there are no pending - * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable - * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS - * is returned signifying master requests disabled. + * Disables PCI-Express primary access and verifies there are no pending + * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable + * bit hasn't caused the primary requests to be disabled, else IXGBE_SUCCESS + * is returned signifying primary requests disabled. **/ -s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) +s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) { s32 status = IXGBE_SUCCESS; u32 i, poll; u16 value; - DEBUGFUNC("ixgbe_disable_pcie_master"); + DEBUGFUNC("ixgbe_disable_pcie_primary"); /* Always set this bit to ensure any future transactions are blocked */ IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); - /* Exit if master requests are blocked */ + /* Exit if primary requests are blocked */ if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || IXGBE_REMOVED(hw->hw_addr)) goto out; - /* Poll for master request bit to clear */ - for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { + /* Poll for primary request bit to clear */ + for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) { usec_delay(100); if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) goto out; @@ -3241,13 +3241,13 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) /* * Two consecutive resets are required via CTRL.RST per datasheet - * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine - * of this need. The first reset prevents new master requests from + * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine + * of this need. The first reset prevents new primary requests from * being issued by our device. We then must wait 1usec or more for any * remaining completions from the PCIe bus to trickle in, and then reset * again to clear out any effects they may have had on our device. */ - DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); + DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n"); hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; if (hw->mac.type >= ixgbe_mac_X550) @@ -3269,7 +3269,7 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) ERROR_REPORT1(IXGBE_ERROR_POLLING, "PCIe transaction pending bit also did not clear.\n"); - status = IXGBE_ERR_MASTER_REQUESTS_PENDING; + status = IXGBE_ERR_PRIMARY_REQUESTS_PENDING; out: return status; diff --git a/sys/dev/ixgbe/ixgbe_common.h b/sys/dev/ixgbe/ixgbe_common.h index a55003b4cfe4..0ff5c60d40af 100644 --- a/sys/dev/ixgbe/ixgbe_common.h +++ b/sys/dev/ixgbe/ixgbe_common.h @@ -118,7 +118,7 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw); s32 ixgbe_validate_mac_addr(u8 *mac_addr); s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); -s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); +s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw); s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); diff --git a/sys/dev/ixgbe/ixgbe_type.h b/sys/dev/ixgbe/ixgbe_type.h index 56d4863c8e07..f34bf8dace64 100644 --- a/sys/dev/ixgbe/ixgbe_type.h +++ b/sys/dev/ixgbe/ixgbe_type.h @@ -1488,7 +1488,7 @@ struct ixgbe_dmac_config { #define IXGBE_PSRTYPE_RQPL_SHIFT 29 /* CTRL Bit Masks */ -#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ +#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Primary Disable bit */ #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) @@ -2136,7 +2136,7 @@ enum { /* STATUS Bit Masks */ #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ -#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ +#define IXGBE_STATUS_GIO 0x00080000 /* GIO Primary Ena Status */ #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ @@ -2546,8 +2546,8 @@ enum { #define IXGBE_PCIDEVCTRL2_4_8s 0xd #define IXGBE_PCIDEVCTRL2_17_34s 0xe -/* Number of 100 microseconds we wait for PCI Express master disable */ -#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 +/* Number of 100 microseconds we wait for PCI Express primary disable */ +#define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT 800 /* Check whether address is multicast. This is little-endian specific check.*/ #define IXGBE_IS_MULTICAST(Address) \ @@ -4221,7 +4221,7 @@ struct ixgbe_hw { #define IXGBE_ERR_ADAPTER_STOPPED -9 #define IXGBE_ERR_INVALID_MAC_ADDR -10 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 -#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 +#define IXGBE_ERR_PRIMARY_REQUESTS_PENDING -12 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 #define IXGBE_ERR_RESET_FAILED -15
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