Date: Sat, 2 Jan 2016 22:04:37 +0000 (UTC) From: Andreas Tobler <andreast@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r293062 - head/sys/powerpc/aim Message-ID: <201601022204.u02M4bAw029329@repo.freebsd.org>
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Author: andreast Date: Sat Jan 2 22:04:37 2016 New Revision: 293062 URL: https://svnweb.freebsd.org/changeset/base/293062 Log: Fix booting of 32-bit kernels on 64-bit G5 hardware. For rs6000, most memory insns and addi/addis do not allow GPR0 for RA (they use literal zero there instead). So use a 'b' constraint to make sure to have a base register other than GPR0. GCC-4.7 and up handles this with allocating r9 instead of r0. Modified: head/sys/powerpc/aim/mp_cpudep.c Modified: head/sys/powerpc/aim/mp_cpudep.c ============================================================================== --- head/sys/powerpc/aim/mp_cpudep.c Sat Jan 2 22:00:52 2016 (r293061) +++ head/sys/powerpc/aim/mp_cpudep.c Sat Jan 2 22:04:37 2016 (r293062) @@ -77,10 +77,10 @@ cpudep_ap_early_bootstrap(void) #else __asm __volatile("ld %0, 16(%2); sync; isync; \ mtspr %1, %0; sync; isync;" - : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state)); __asm __volatile("ld %0, 24(%2); sync; isync; \ mtspr %1, %0; sync; isync;" - : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state)); #endif powerpc_sync(); break; @@ -324,10 +324,10 @@ cpudep_ap_setup() mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ sync; isync" - : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state)); __asm __volatile("ld %0, 8(%2); sync; isync; \ mtspr %1, %0; mtspr %1, %0; sync; isync" - : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state)); #endif powerpc_sync();
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