Date: Mon, 26 Aug 2024 00:52:28 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: 0d1946282654 - main - cad/verilator: update 5.026 =?utf-8?Q?=E2=86=92?= 5.028 Message-ID: <202408260052.47Q0qSaJ090089@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=0d194628265496d359adb37c475cf47123c73b0c commit 0d194628265496d359adb37c475cf47123c73b0c Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2024-08-25 18:16:43 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2024-08-26 00:52:21 +0000 cad/verilator: update 5.026 → 5.028 Reported by: portscout --- cad/verilator/Makefile | 2 +- cad/verilator/distinfo | 6 +++--- cad/verilator/files/patch-src-verilog.y | 10 ---------- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile index ea078ecbbde2..c346ee9fe055 100644 --- a/cad/verilator/Makefile +++ b/cad/verilator/Makefile @@ -1,6 +1,6 @@ PORTNAME= verilator DISTVERSIONPREFIX= v -DISTVERSION= 5.026 +DISTVERSION= 5.028 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo index 20b22d3e8357..9662da6d7118 100644 --- a/cad/verilator/distinfo +++ b/cad/verilator/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1718513016 -SHA256 (verilator-verilator-v5.026_GH0.tar.gz) = 87fdecf3967007d9ee8c30191ff2476f2a33635d0e0c6e3dbf345cc2f0c50b78 -SIZE (verilator-verilator-v5.026_GH0.tar.gz) = 3931397 +TIMESTAMP = 1724606521 +SHA256 (verilator-verilator-v5.028_GH0.tar.gz) = 02d4b6f34754b46a97cfd70f5fcbc9b730bd1f0a24c3fc37223397778fcb142c +SIZE (verilator-verilator-v5.028_GH0.tar.gz) = 32547892 diff --git a/cad/verilator/files/patch-src-verilog.y b/cad/verilator/files/patch-src-verilog.y deleted file mode 100644 index 36fecfa89945..000000000000 --- a/cad/verilator/files/patch-src-verilog.y +++ /dev/null @@ -1,10 +0,0 @@ ---- src/verilog.y.orig 2020-08-14 11:38:09 UTC -+++ src/verilog.y -@@ -31,7 +31,6 @@ - #include <cstdarg> - #include <stack> - --#define YYERROR_VERBOSE 1 // For prior to Bison 3.6 - #define YYINITDEPTH 10000 // Older bisons ignore YYMAXDEPTH - #define YYMAXDEPTH 10000 -
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