Date: Thu, 1 Nov 2012 14:43:21 +0000 From: Attilio Rao <attilio@freebsd.org> To: Ian Lepore <freebsd@damnhippie.dyndns.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, Gleb Smirnoff <glebius@freebsd.org>, src-committers@freebsd.org Subject: Re: svn commit: r242402 - in head/sys: kern vm Message-ID: <CAJ-FndBz=UXKANBkSrtxPUBcYyV4kh0LRm-HyxNbHEhkJd4oqQ@mail.gmail.com> In-Reply-To: <1351780635.1120.135.camel@revolution.hippie.lan> References: <201210311807.q9VI7IcX000993@svn.freebsd.org> <CAJ-FndDRkBS57e9mzZoJWX5ugJ0KBGxhMSO50KB8Wm8MFudjCA@mail.gmail.com> <1351707964.1120.97.camel@revolution.hippie.lan> <CAJ-FndC7QwpNAjzQTumqTY6Sj_RszXPwc0pbHv2-pRGMqbw0ww@mail.gmail.com> <20121101100814.GB70741@FreeBSD.org> <CAJ-FndARMhgCRYwo0%2BS4tZ=At6rHJSz_tsy-OtHRHZKkxL-sig@mail.gmail.com> <1351778472.1120.117.camel@revolution.hippie.lan> <CAJ-FndCpcBTFpsdTLYoadG2P3oZFYq_viGSTNOc7YM5G66FFsg@mail.gmail.com> <CAJ-FndCG6WZ0Rwm9HcJhy4K32%2BC3vai2mQim_q7%2BMd427L6LbQ@mail.gmail.com> <1351780635.1120.135.camel@revolution.hippie.lan>
next in thread | previous in thread | raw e-mail | index | archive | help
On 11/1/12, Ian Lepore <freebsd@damnhippie.dyndns.org> wrote: > On Thu, 2012-11-01 at 14:07 +0000, Attilio Rao wrote: >> On Thu, Nov 1, 2012 at 2:05 PM, Attilio Rao <attilio@freebsd.org> wrote: >> > On Thu, Nov 1, 2012 at 2:01 PM, Ian Lepore >> > <freebsd@damnhippie.dyndns.org> wrote: >> >> On Thu, 2012-11-01 at 10:42 +0000, Attilio Rao wrote: >> >>> On 11/1/12, Gleb Smirnoff <glebius@freebsd.org> wrote: >> >>> > On Wed, Oct 31, 2012 at 06:33:51PM +0000, Attilio Rao wrote: >> >>> > A> > Doesn't this padding to cache line size only help x86 >> >>> > processors in an >> >>> > A> > SMP kernel? I was expecting to see some #ifdef SMP so that we >> >>> > don't >> >>> > pay >> >>> > A> > a big price for no gain in small-memory ARM systems and such. >> >>> > But >> >>> > maybe >> >>> > A> > I'm misunderstanding the reason for the padding. >> >>> > A> >> >>> > A> I didn't want to do this because this would be meaning that SMP >> >>> > option >> >>> > A> may become a completely killer for modules/kernel ABI >> >>> > compatibility. >> >>> > >> >>> > Do we support loading non-SMP modules on SMP kernel and vice versa? >> >>> >> >>> Actually that's my point, we do. >> >>> >> >>> Attilio >> >>> >> >>> >> >> >> >> Well we've got other similar problems lurking then. What about a >> >> module >> >> compiled on an arm system that had #define CACHE_LINE_SIZE 32 and then >> >> it gets run on a different arm system whose kernel is compiled with >> >> #define CACHE_LINE_SIZE 64? >> > >> > That should not happen. Is that a real case where you build a module >> > for an ARM family and want to run against a kernel compiled for >> > another? >> >> Besides that, the ARM CACHE_LINE_SIZE is defined in the shared headers >> so there is no way this can be a problem. > > I've been under the impression that in the ARM and MIPS worlds, the > cache line size can change from one family/series of chips to another, > just as support for SMP can change from one family to another. If I'm > not mistaken in that assumption, then there can't be something like a > generic arm module that will run on any arm kernel regardless of how the > kernel was built, not if compile-time constants get cooked into the > binaries in a way that affects the ABI/KBI. I'm far from being an ARM expert so I trust what you say. This only means you cannot build a module for a family and expect to retain ABI compatibility among all the ARM families. If cache-lines are different I don't think there is much we can do, which has nothing to do with pad-align locking. Attilio -- Peace can only be achieved by understanding - A. Einstein
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?CAJ-FndBz=UXKANBkSrtxPUBcYyV4kh0LRm-HyxNbHEhkJd4oqQ>