Date: Thu, 7 Sep 2023 20:39:32 -0600 From: John Nielsen <lists@jnielsen.net> To: Adrian Chadd <adrian@freebsd.org> Cc: "Bjoern A. Zeeb" <bzeeb-lists@lists.zabbadoz.net>, wireless@freebsd.org Subject: Re: Help me grok the ath(4) device attach code Message-ID: <92D595F6-C268-4E61-BB3E-51DC5F8B6961@jnielsen.net> In-Reply-To: <CAJ-Vmo=HR8=nvFLPQTG=2NZCCuV_bsLY67cgGo=FdLoT%2BvbnZQ@mail.gmail.com>
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<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div dir="ltr"></div><div dir="ltr">Coming back to this after a busy couple of months..</div><div dir="ltr"><br><blockquote type="cite">On Jun 11, 2023, at 9:48 PM, Adrian Chadd <adrian@freebsd.org> wrote:<br></blockquote></div><blockquote type="cite"><div dir="ltr"><div dir="ltr"><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sun, 11 Jun 2023 at 18:17, John Nielsen <<a href="mailto:lists@jnielsen.net">lists@jnielsen.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">> On May 30, 2023, at 11:17 PM, Adrian Chadd <<a href="mailto:adrian@freebsd.org" target="_blank">adrian@freebsd.org</a>> wrote:<br> > <br> > There's known issues with all the Atheros chips (sigh) with how the EEPROM and PCIe bus reset .. interact.<br> > (If the bus reset is too short then the EEPROM state machine gets stuck and nothing gets read.) It makes debugging this hard because the NIC itself will work in another device fine, because it's the BIOS/ACPI code. :(<br></blockquote></div></div></div></blockquote><div><br></div><div>Are these “known issues” documented anywhere public?</div><br><blockquote type="cite"><div dir="ltr"><div dir="ltr"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> Does “nothing gets read” manifest as getting zeroes back? That does appear to be what’s happening on my laptop:<br></blockquote><div><br></div><div>Yeah that's not a good sign.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> Trying (2) EEPROM access at address 0x03ff<br> ar9300_eeprom_restore_internal_address: Found block at 3ff: code=0 ref=0 length=0 major=0 minor=0<br> ar9300_eeprom_restore_internal_address: word[0]=0x00 word[1]=0x00 word[2]=0x00 word[3]=0x00<br> ar9300_eeprom_restore_internal_address: checksum 0 0<br> ar9300_eeprom_restore_internal_address: EEPROM structure size mismatch memory=1088 eeprom=0<br> <br> Are there any workarounds (even gross ones like sleeping 2 seconds somewhere)?<br></blockquote><div><br></div><div>The gross workaround is to manually reset the pcie RC/EP and do it for the right amount of time. ;-)</div></div></div> </div></blockquote><br><div>How/where would I do a proof of concept of this gross workaround? Sprinkle in pcie_link_reset() somewhere? Or is it more of a rewrite of the bus initialization code?</div><div><br></div><div><br></div><div>Thanks,</div><div><br></div><div>JN</div><div><br></div></body></html>home | help
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