Date: Mon, 25 May 2015 13:43:03 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r283526 - in head: . contrib/llvm/include/llvm/Target contrib/llvm/lib/Analysis contrib/llvm/lib/CodeGen contrib/llvm/lib/CodeGen/SelectionDAG contrib/llvm/lib/ExecutionEngine/RuntimeDy... Message-ID: <201505251343.t4PDh3wR037780@svn.freebsd.org>
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Author: dim Date: Mon May 25 13:43:03 2015 New Revision: 283526 URL: https://svnweb.freebsd.org/changeset/base/283526 Log: Upgrade our copy of clang and llvm to 3.6.1 release. This release contains the following cherry-picked revisions from upstream trunk: 226124 226151 226164 226165 226166 226407 226408 226409 226652 226905 226983 227084 227087 227089 227208 227209 227210 227211 227212 227213 227214 227269 227430 227482 227503 227519 227574 227822 227986 227987 227988 227989 227990 228037 228038 228039 228040 228188 228189 228190 228273 228372 228373 228374 228403 228765 228848 228918 229223 229225 229226 229227 229228 229230 229234 229235 229236 229238 229239 229413 229507 229680 229750 229751 229752 229911 230146 230147 230235 230253 230255 230469 230500 230564 230603 230657 230742 230748 230956 231219 231237 231245 231259 231280 231451 231563 231601 231658 231659 231662 231984 231986 232046 232085 232142 232176 232179 232189 232382 232386 232389 232425 232438 232443 232675 232786 232797 232943 232957 233075 233080 233351 233353 233409 233410 233508 233584 233819 233904 234629 234636 234891 234975 234977 235524 235641 235662 235931 236099 236306 236307 Please note that from 3.5.0 onwards, clang and llvm require C++11 support to build; see UPDATING for more information. Added: head/contrib/llvm/patches/patch-08-llvm-r230348-arm-fix-bad-ha.diff - copied, changed from r283525, head/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff head/contrib/llvm/patches/patch-09-clang-r227115-constantarraytype.diff - copied unchanged from r283313, head/contrib/llvm/patches/patch-12-clang-r227115-constantarraytype.diff Deleted: head/contrib/llvm/patches/patch-08-llvm-r227089-fix-mips-i128.diff head/contrib/llvm/patches/patch-09-llvm-r230058-indirectbrs-assert.diff head/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff head/contrib/llvm/patches/patch-11-llvm-r231227-aarch64-tls-relocs.diff head/contrib/llvm/patches/patch-12-clang-r227115-constantarraytype.diff head/contrib/llvm/patches/patch-13-llvm-r229911-uleb128-commas.diff Modified: head/ObsoleteFiles.inc head/UPDATING head/contrib/llvm/include/llvm/Target/TargetCallingConv.h head/contrib/llvm/include/llvm/Target/TargetLowering.h head/contrib/llvm/lib/Analysis/ScalarEvolutionExpander.cpp head/contrib/llvm/lib/CodeGen/MachineCopyPropagation.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp head/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp head/contrib/llvm/lib/IR/ConstantFold.cpp head/contrib/llvm/lib/IR/GCOV.cpp head/contrib/llvm/lib/Support/Unix/Memory.inc head/contrib/llvm/lib/Support/Windows/explicit_symbols.inc head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp head/contrib/llvm/lib/Target/Mips/Mips.td head/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp head/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td head/contrib/llvm/lib/Target/Mips/MipsCCState.cpp head/contrib/llvm/lib/Target/Mips/MipsCallingConv.td head/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td head/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.td head/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp head/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp head/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp head/contrib/llvm/lib/Target/R600/AMDGPU.td head/contrib/llvm/lib/Target/R600/AMDGPUAlwaysInlinePass.cpp head/contrib/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp head/contrib/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp head/contrib/llvm/lib/Target/R600/AMDGPUISelLowering.cpp head/contrib/llvm/lib/Target/R600/AMDGPUInstrInfo.h head/contrib/llvm/lib/Target/R600/AMDGPUInstrInfo.td head/contrib/llvm/lib/Target/R600/AMDGPUInstructions.td head/contrib/llvm/lib/Target/R600/AMDGPUIntrinsics.td head/contrib/llvm/lib/Target/R600/AMDGPUSubtarget.cpp head/contrib/llvm/lib/Target/R600/AMDGPUSubtarget.h head/contrib/llvm/lib/Target/R600/CaymanInstructions.td head/contrib/llvm/lib/Target/R600/EvergreenInstructions.td head/contrib/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp head/contrib/llvm/lib/Target/R600/Processors.td head/contrib/llvm/lib/Target/R600/R600ISelLowering.cpp head/contrib/llvm/lib/Target/R600/R600Instructions.td head/contrib/llvm/lib/Target/R600/SIAnnotateControlFlow.cpp head/contrib/llvm/lib/Target/R600/SIDefines.h head/contrib/llvm/lib/Target/R600/SIFoldOperands.cpp head/contrib/llvm/lib/Target/R600/SIISelLowering.cpp head/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp head/contrib/llvm/lib/Target/R600/SIInstrFormats.td head/contrib/llvm/lib/Target/R600/SIInstrInfo.cpp head/contrib/llvm/lib/Target/R600/SIInstrInfo.h head/contrib/llvm/lib/Target/R600/SIInstrInfo.td head/contrib/llvm/lib/Target/R600/SIInstructions.td head/contrib/llvm/lib/Target/R600/SILowerControlFlow.cpp head/contrib/llvm/lib/Target/R600/SIRegisterInfo.cpp head/contrib/llvm/lib/Target/R600/SIRegisterInfo.h head/contrib/llvm/lib/Target/R600/SIRegisterInfo.td head/contrib/llvm/lib/Target/R600/VIInstrFormats.td head/contrib/llvm/lib/Target/R600/VIInstructions.td head/contrib/llvm/lib/Target/X86/X86FrameLowering.cpp head/contrib/llvm/lib/Target/X86/X86FrameLowering.h head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp head/contrib/llvm/lib/Target/X86/X86InstrControl.td head/contrib/llvm/lib/Target/X86/X86IntrinsicsInfo.h head/contrib/llvm/lib/Transforms/Instrumentation/GCOVProfiling.cpp head/contrib/llvm/lib/Transforms/Scalar/GVN.cpp head/contrib/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp head/contrib/llvm/patches/README.TXT head/contrib/llvm/patches/patch-01-freebsd-kprintf.diff head/contrib/llvm/patches/patch-07-llvm-r227752-boot2-shrink.diff head/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td head/contrib/llvm/tools/clang/include/clang/Basic/TargetCXXABI.h head/contrib/llvm/tools/clang/include/clang/Basic/TargetInfo.h head/contrib/llvm/tools/clang/include/clang/Sema/Sema.h head/contrib/llvm/tools/clang/include/clang/Sema/Template.h head/contrib/llvm/tools/clang/lib/AST/ASTContext.cpp head/contrib/llvm/tools/clang/lib/AST/ASTDiagnostic.cpp head/contrib/llvm/tools/clang/lib/AST/Decl.cpp head/contrib/llvm/tools/clang/lib/Analysis/ThreadSafety.cpp head/contrib/llvm/tools/clang/lib/Basic/SourceManager.cpp head/contrib/llvm/tools/clang/lib/Basic/TargetInfo.cpp head/contrib/llvm/tools/clang/lib/Basic/Targets.cpp head/contrib/llvm/tools/clang/lib/Basic/Version.cpp head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp head/contrib/llvm/tools/clang/lib/CodeGen/ItaniumCXXABI.cpp head/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp head/contrib/llvm/tools/clang/lib/Frontend/InitPreprocessor.cpp head/contrib/llvm/tools/clang/lib/Sema/DeclSpec.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaChecking.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaExpr.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaExprCXX.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaTemplate.cpp head/etc/mtree/BSD.debug.dist head/etc/mtree/BSD.usr.dist head/lib/clang/include/Makefile head/lib/clang/include/clang/Basic/Version.inc head/lib/clang/include/clang/Config/config.h head/lib/clang/include/llvm/Config/config.h head/lib/clang/include/llvm/Config/llvm-config.h head/lib/libclang_rt/Makefile.inc head/sys/sys/param.h head/tools/build/mk/OptionalObsoleteFiles.inc Directory Properties: head/contrib/llvm/ (props changed) head/contrib/llvm/tools/clang/ (props changed) Modified: head/ObsoleteFiles.inc ============================================================================== --- head/ObsoleteFiles.inc Mon May 25 11:56:57 2015 (r283525) +++ head/ObsoleteFiles.inc Mon May 25 13:43:03 2015 (r283526) @@ -38,6 +38,67 @@ # xargs -n1 | sort | uniq -d; # done +# 20150525: new clang import which bumps version from 3.6.0 to 3.6.1. +OLD_FILES+=usr/lib/clang/3.6.0/include/__stddef_max_align_t.h +OLD_FILES+=usr/lib/clang/3.6.0/include/__wmmintrin_aes.h +OLD_FILES+=usr/lib/clang/3.6.0/include/__wmmintrin_pclmul.h +OLD_FILES+=usr/lib/clang/3.6.0/include/adxintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/altivec.h +OLD_FILES+=usr/lib/clang/3.6.0/include/ammintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/arm_acle.h +OLD_FILES+=usr/lib/clang/3.6.0/include/arm_neon.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx2intrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx512bwintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx512erintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx512fintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx512vlbwintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avx512vlintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/avxintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/bmi2intrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/bmiintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/cpuid.h +OLD_FILES+=usr/lib/clang/3.6.0/include/emmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/f16cintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/fma4intrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/fmaintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/ia32intrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/immintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/lzcntintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/mm3dnow.h +OLD_FILES+=usr/lib/clang/3.6.0/include/mm_malloc.h +OLD_FILES+=usr/lib/clang/3.6.0/include/mmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/module.modulemap +OLD_FILES+=usr/lib/clang/3.6.0/include/nmmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/pmmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/popcntintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/prfchwintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/rdseedintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/rtmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/shaintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/smmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/tbmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/tmmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/wmmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/x86intrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/xmmintrin.h +OLD_FILES+=usr/lib/clang/3.6.0/include/xopintrin.h +OLD_DIRS+=usr/lib/clang/3.6.0/include +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.asan-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.asan-x86_64.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.asan_cxx-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.profile-arm.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.profile-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.profile-x86_64.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.san-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.san-x86_64.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.ubsan-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.ubsan-x86_64.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.ubsan_cxx-i386.a +OLD_FILES+=usr/lib/clang/3.6.0/lib/freebsd/libclang_rt.ubsan_cxx-x86_64.a +OLD_DIRS+=usr/lib/clang/3.6.0/lib/freebsd +OLD_DIRS+=usr/lib/clang/3.6.0/lib +OLD_DIRS+=usr/lib/clang/3.6.0 # 20150521 OLD_FILES+=usr/bin/demandoc OLD_FILES+=usr/share/man/man1/demandoc.1.gz Modified: head/UPDATING ============================================================================== --- head/UPDATING Mon May 25 11:56:57 2015 (r283525) +++ head/UPDATING Mon May 25 13:43:03 2015 (r283526) @@ -31,6 +31,11 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11 disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20150525: + Clang and llvm have been upgraded to 3.6.1 release. Please see the + 20141231 entry below for information about prerequisites and upgrading, + if you are not already using 3.5.0 or higher. + 20150521: TI platform code switched to using vendor DTS files and this update may break existing systems running on Beaglebone, Beaglebone Black, Modified: head/contrib/llvm/include/llvm/Target/TargetCallingConv.h ============================================================================== --- head/contrib/llvm/include/llvm/Target/TargetCallingConv.h Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/include/llvm/Target/TargetCallingConv.h Mon May 25 13:43:03 2015 (r283526) @@ -134,6 +134,8 @@ namespace ISD { /// Index original Function's argument. unsigned OrigArgIndex; + /// Sentinel value for implicit machine-level input arguments. + static const unsigned NoArgIndex = UINT_MAX; /// Offset in bytes of current input value relative to the beginning of /// original argument. E.g. if argument was splitted into four 32 bit @@ -147,6 +149,15 @@ namespace ISD { VT = vt.getSimpleVT(); ArgVT = argvt; } + + bool isOrigArg() const { + return OrigArgIndex != NoArgIndex; + } + + unsigned getOrigArgIndex() const { + assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument"); + return OrigArgIndex; + } }; /// OutputArg - This struct carries flags and a value for a Modified: head/contrib/llvm/include/llvm/Target/TargetLowering.h ============================================================================== --- head/contrib/llvm/include/llvm/Target/TargetLowering.h Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/include/llvm/Target/TargetLowering.h Mon May 25 13:43:03 2015 (r283526) @@ -2806,6 +2806,11 @@ public: virtual bool useLoadStackGuardNode() const { return false; } + + /// Returns true if arguments should be sign-extended in lib calls. + virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + return IsSigned; + } }; /// Given an LLVM IR type and return type attributes, compute the return value Modified: head/contrib/llvm/lib/Analysis/ScalarEvolutionExpander.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/ScalarEvolutionExpander.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Analysis/ScalarEvolutionExpander.cpp Mon May 25 13:43:03 2015 (r283526) @@ -1776,9 +1776,12 @@ unsigned SCEVExpander::replaceCongruentI << *IsomorphicInc << '\n'); Value *NewInc = OrigInc; if (OrigInc->getType() != IsomorphicInc->getType()) { - Instruction *IP = isa<PHINode>(OrigInc) - ? (Instruction*)L->getHeader()->getFirstInsertionPt() - : OrigInc->getNextNode(); + Instruction *IP = nullptr; + if (PHINode *PN = dyn_cast<PHINode>(OrigInc)) + IP = PN->getParent()->getFirstInsertionPt(); + else + IP = OrigInc->getNextNode(); + IRBuilder<> Builder(IP); Builder.SetCurrentDebugLocation(IsomorphicInc->getDebugLoc()); NewInc = Builder. Modified: head/contrib/llvm/lib/CodeGen/MachineCopyPropagation.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/MachineCopyPropagation.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/MachineCopyPropagation.cpp Mon May 25 13:43:03 2015 (r283526) @@ -75,10 +75,9 @@ MachineCopyPropagation::SourceNoLongerAv I != E; ++I) { unsigned MappedDef = *I; // Source of copy is no longer available for propagation. - if (AvailCopyMap.erase(MappedDef)) { - for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) - AvailCopyMap.erase(*SR); - } + AvailCopyMap.erase(MappedDef); + for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) + AvailCopyMap.erase(*SR); } } } Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 25 13:43:03 2015 (r283526) @@ -1160,13 +1160,6 @@ void DAGCombiner::Run(CombineLevel AtLev LegalOperations = Level >= AfterLegalizeVectorOps; LegalTypes = Level >= AfterLegalizeTypes; - // Early exit if this basic block is in an optnone function. - AttributeSet FnAttrs = - DAG.getMachineFunction().getFunction()->getAttributes(); - if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex, - Attribute::OptimizeNone)) - return; - // Add all the dag nodes to the worklist. for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I) @@ -2788,9 +2781,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) SplatBitSize = SplatBitSize * 2) SplatValue |= SplatValue.shl(SplatBitSize); - Constant = APInt::getAllOnesValue(BitWidth); - for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) - Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); + // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a + // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value. + if (SplatBitSize % BitWidth == 0) { + Constant = APInt::getAllOnesValue(BitWidth); + for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) + Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); + } } } @@ -11043,7 +11040,9 @@ SDValue DAGCombiner::visitBUILD_VECTOR(S } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) { // If the input vector is too large, try to split it. // We don't support having two input vectors that are too large. - if (VecIn2.getNode()) + // If the zero vector was used, we can not split the vector, + // since we'd need 3 inputs. + if (UsesZeroVector || VecIn2.getNode()) return SDValue(); if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements())) @@ -11055,7 +11054,6 @@ SDValue DAGCombiner::visitBUILD_VECTOR(S DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy())); VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1, DAG.getConstant(0, TLI.getVectorIdxTy())); - UsesZeroVector = false; } else return SDValue(); } Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp Mon May 25 13:43:03 2015 (r283526) @@ -497,7 +497,7 @@ bool FastISel::selectGetElementPtr(const OI != E; ++OI) { const Value *Idx = *OI; if (auto *StTy = dyn_cast<StructType>(Ty)) { - unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); + uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue(); if (Field) { // N = N + Offset TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field); @@ -518,8 +518,8 @@ bool FastISel::selectGetElementPtr(const if (CI->isZero()) continue; // N = N + Offset - TotalOffs += - DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue(); + uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue(); + TotalOffs += DL.getTypeAllocSize(Ty) * IdxN; if (TotalOffs >= MaxOffs) { N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); if (!N) // Unhandled operand. Halt "fast" selection and bail. Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon May 25 13:43:03 2015 (r283526) @@ -658,7 +658,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes NVT, N->getOperand(0)); return TLI.makeLibCall(DAG, LC, TLI.getTypeToTransformTo(*DAG.getContext(), RVT), - &Op, 1, false, dl).first; + &Op, 1, Signed, dl).first; } Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon May 25 13:43:03 2015 (r283526) @@ -1423,9 +1423,10 @@ SUnit *ScheduleDAGRRList::PickNodeToSche // If one or more successors has been unscheduled, then the current // node is no longer available. - if (!TrySU->isAvailable) + if (!TrySU->isAvailable || !TrySU->NodeQueueId) CurSU = AvailableQueue->pop(); else { + // Available and in AvailableQueue AvailableQueue->remove(TrySU); CurSU = TrySU; } Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon May 25 13:43:03 2015 (r283526) @@ -3399,30 +3399,21 @@ void SelectionDAGBuilder::visitGetElemen Ty = StTy->getElementType(Field); } else { Ty = cast<SequentialType>(Ty)->getElementType(); + MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS); + unsigned PtrSize = PtrTy.getSizeInBits(); + APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty)); // If this is a constant subscript, handle it quickly. - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { - if (CI->isZero()) continue; - uint64_t Offs = - DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); - SDValue OffsVal; - EVT PTy = TLI.getPointerTy(AS); - unsigned PtrBits = PTy.getSizeInBits(); - if (PtrBits < 64) - OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy, - DAG.getConstant(Offs, MVT::i64)); - else - OffsVal = DAG.getConstant(Offs, PTy); - - N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, - OffsVal); + if (const auto *CI = dyn_cast<ConstantInt>(Idx)) { + if (CI->isZero()) + continue; + APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize); + SDValue OffsVal = DAG.getConstant(Offs, PtrTy); + N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal); continue; } // N = N + Idx * ElementSize; - APInt ElementSize = - APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty)); SDValue IdxN = getValue(Idx); // If the index is smaller or larger than intptr_t, truncate or extend @@ -5727,6 +5718,11 @@ void SelectionDAGBuilder::LowerCallTo(Im // Skip the first return-type Attribute to get to params. Entry.setAttributes(&CS, i - CS.arg_begin() + 1); Args.push_back(Entry); + + // If we have an explicit sret argument that is an Instruction, (i.e., it + // might point to function-local memory), we can't meaningfully tail-call. + if (Entry.isSRet && isa<Instruction>(V)) + isTailCall = false; } // Check if target-independent constraints permit a tail call here. @@ -7353,6 +7349,10 @@ TargetLowering::LowerCallTo(TargetLoweri Entry.Alignment = Align; CLI.getArgs().insert(CLI.getArgs().begin(), Entry); CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext()); + + // sret demotion isn't compatible with tail-calls, since the sret argument + // points into the callers stack frame. + CLI.IsTailCall = false; } else { for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { EVT VT = RetTys[I]; @@ -7638,7 +7638,8 @@ void SelectionDAGISel::LowerArguments(co ISD::ArgFlagsTy Flags; Flags.setSRet(); MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); - ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0); + ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, + ISD::InputArg::NoArgIndex, 0); Ins.push_back(RetArg); } Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon May 25 13:43:03 2015 (r283526) @@ -96,18 +96,19 @@ TargetLowering::makeLibCall(SelectionDAG for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); - Entry.isSExt = isSigned; - Entry.isZExt = !isSigned; + Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); + Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned); Args.push_back(Entry); } SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); + bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0) .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed) - .setSExtResult(isSigned).setZExtResult(!isSigned); + .setSExtResult(signExtend).setZExtResult(!signExtend); return LowerCallTo(CLI); } Modified: head/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp ============================================================================== --- head/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Mon May 25 13:43:03 2015 (r283526) @@ -177,25 +177,30 @@ bool RuntimeDyldMachO::isCompatibleFile( } template <typename Impl> -void RuntimeDyldMachOCRTPBase<Impl>::finalizeLoad(const ObjectFile &ObjImg, +void RuntimeDyldMachOCRTPBase<Impl>::finalizeLoad(const ObjectFile &Obj, ObjSectionToIDMap &SectionMap) { unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID; unsigned TextSID = RTDYLD_INVALID_SECTION_ID; unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID; - ObjSectionToIDMap::iterator i, e; - for (i = SectionMap.begin(), e = SectionMap.end(); i != e; ++i) { - const SectionRef &Section = i->first; + for (const auto &Section : Obj.sections()) { StringRef Name; Section.getName(Name); - if (Name == "__eh_frame") - EHFrameSID = i->second; - else if (Name == "__text") - TextSID = i->second; + + // Force emission of the __text, __eh_frame, and __gcc_except_tab sections + // if they're present. Otherwise call down to the impl to handle other + // sections that have already been emitted. + if (Name == "__text") + TextSID = findOrEmitSection(Obj, Section, true, SectionMap); + else if (Name == "__eh_frame") + EHFrameSID = findOrEmitSection(Obj, Section, false, SectionMap); else if (Name == "__gcc_except_tab") - ExceptTabSID = i->second; - else - impl().finalizeSection(ObjImg, i->second, Section); + ExceptTabSID = findOrEmitSection(Obj, Section, true, SectionMap); + else { + auto I = SectionMap.find(Section); + if (I != SectionMap.end()) + impl().finalizeSection(Obj, I->second, Section); + } } UnregisteredEHFrameSections.push_back( EHFrameRelatedSections(EHFrameSID, TextSID, ExceptTabSID)); @@ -238,7 +243,8 @@ unsigned char *RuntimeDyldMachOCRTPBase< } static int64_t computeDelta(SectionEntry *A, SectionEntry *B) { - int64_t ObjDistance = A->ObjAddress - B->ObjAddress; + int64_t ObjDistance = + static_cast<int64_t>(A->ObjAddress) - static_cast<int64_t>(B->ObjAddress); int64_t MemDistance = A->LoadAddress - B->LoadAddress; return ObjDistance - MemDistance; } Modified: head/contrib/llvm/lib/IR/ConstantFold.cpp ============================================================================== --- head/contrib/llvm/lib/IR/ConstantFold.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/IR/ConstantFold.cpp Mon May 25 13:43:03 2015 (r283526) @@ -1120,27 +1120,18 @@ Constant *llvm::ConstantFoldBinaryInstru return ConstantInt::get(CI1->getContext(), C1V | C2V); case Instruction::Xor: return ConstantInt::get(CI1->getContext(), C1V ^ C2V); - case Instruction::Shl: { - uint32_t shiftAmt = C2V.getZExtValue(); - if (shiftAmt < C1V.getBitWidth()) - return ConstantInt::get(CI1->getContext(), C1V.shl(shiftAmt)); - else - return UndefValue::get(C1->getType()); // too big shift is undef - } - case Instruction::LShr: { - uint32_t shiftAmt = C2V.getZExtValue(); - if (shiftAmt < C1V.getBitWidth()) - return ConstantInt::get(CI1->getContext(), C1V.lshr(shiftAmt)); - else - return UndefValue::get(C1->getType()); // too big shift is undef - } - case Instruction::AShr: { - uint32_t shiftAmt = C2V.getZExtValue(); - if (shiftAmt < C1V.getBitWidth()) - return ConstantInt::get(CI1->getContext(), C1V.ashr(shiftAmt)); - else - return UndefValue::get(C1->getType()); // too big shift is undef - } + case Instruction::Shl: + if (C2V.ult(C1V.getBitWidth())) + return ConstantInt::get(CI1->getContext(), C1V.shl(C2V)); + return UndefValue::get(C1->getType()); // too big shift is undef + case Instruction::LShr: + if (C2V.ult(C1V.getBitWidth())) + return ConstantInt::get(CI1->getContext(), C1V.lshr(C2V)); + return UndefValue::get(C1->getType()); // too big shift is undef + case Instruction::AShr: + if (C2V.ult(C1V.getBitWidth())) + return ConstantInt::get(CI1->getContext(), C1V.ashr(C2V)); + return UndefValue::get(C1->getType()); // too big shift is undef } } Modified: head/contrib/llvm/lib/IR/GCOV.cpp ============================================================================== --- head/contrib/llvm/lib/IR/GCOV.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/IR/GCOV.cpp Mon May 25 13:43:03 2015 (r283526) @@ -263,10 +263,12 @@ bool GCOVFunction::readGCDA(GCOVBuffer & // required to combine the edge counts that are contained in the GCDA file. for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) { // The last block is always reserved for exit block - if (BlockNo >= Blocks.size()-1) { + if (BlockNo >= Blocks.size()) { errs() << "Unexpected number of edges (in " << Name << ").\n"; return false; } + if (BlockNo == Blocks.size() - 1) + errs() << "(" << Name << ") has arcs from exit block.\n"; GCOVBlock &Block = *Blocks[BlockNo]; for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End; ++EdgeNo) { Modified: head/contrib/llvm/lib/Support/Unix/Memory.inc ============================================================================== --- head/contrib/llvm/lib/Support/Unix/Memory.inc Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Support/Unix/Memory.inc Mon May 25 13:43:03 2015 (r283526) @@ -333,23 +333,12 @@ void Memory::InvalidateInstructionCache( for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize) asm volatile("icbi 0, %0" : : "r"(Line)); asm volatile("isync"); -# elif (defined(__arm__) || defined(__aarch64__)) && defined(__GNUC__) +# elif (defined(__arm__) || defined(__aarch64__) || defined(__mips__)) && \ + defined(__GNUC__) // FIXME: Can we safely always call this for __GNUC__ everywhere? const char *Start = static_cast<const char *>(Addr); const char *End = Start + Len; __clear_cache(const_cast<char *>(Start), const_cast<char *>(End)); -# elif defined(__mips__) - const char *Start = static_cast<const char *>(Addr); -# if defined(ANDROID) - // The declaration of "cacheflush" in Android bionic: - // extern int cacheflush(long start, long end, long flags); - const char *End = Start + Len; - long LStart = reinterpret_cast<long>(const_cast<char *>(Start)); - long LEnd = reinterpret_cast<long>(const_cast<char *>(End)); - cacheflush(LStart, LEnd, BCACHE); -# else - cacheflush(const_cast<char *>(Start), Len, BCACHE); -# endif # endif #endif // end apple Modified: head/contrib/llvm/lib/Support/Windows/explicit_symbols.inc ============================================================================== --- head/contrib/llvm/lib/Support/Windows/explicit_symbols.inc Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Support/Windows/explicit_symbols.inc Mon May 25 13:43:03 2015 (r283526) @@ -10,9 +10,15 @@ #ifdef HAVE___CHKSTK EXPLICIT_SYMBOL(__chkstk) #endif +#ifdef HAVE___CHKSTK_MS + EXPLICIT_SYMBOL(__chkstk_ms) +#endif #ifdef HAVE____CHKSTK EXPLICIT_SYMBOL(___chkstk) #endif +#ifdef HAVE____CHKSTK_MS + EXPLICIT_SYMBOL(___chkstk_ms) +#endif #ifdef HAVE___MAIN EXPLICIT_SYMBOL(__main) // FIXME: Don't call it. #endif Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Mon May 25 13:43:03 2015 (r283526) @@ -2031,18 +2031,19 @@ SDValue AArch64TargetLowering::LowerForm unsigned CurArgIdx = 0; for (unsigned i = 0; i != NumArgs; ++i) { MVT ValVT = Ins[i].VT; - std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx); - CurArgIdx = Ins[i].OrigArgIndex; - - // Get type of the original argument. - EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true); - MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other; - // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. - if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) - ValVT = MVT::i8; - else if (ActualMVT == MVT::i16) - ValVT = MVT::i16; + if (Ins[i].isOrigArg()) { + std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + // Get type of the original argument. + EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true); + MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other; + // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. + if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) + ValVT = MVT::i8; + else if (ActualMVT == MVT::i16) + ValVT = MVT::i16; + } CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo); Modified: head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Mon May 25 13:43:03 2015 (r283526) @@ -3092,8 +3092,11 @@ ARMTargetLowering::LowerFormalArguments( for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx); - CurArgIdx = Ins[VA.getValNo()].OrigArgIndex; + if (Ins[VA.getValNo()].isOrigArg()) { + std::advance(CurOrigArg, + Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex(); + } // Arguments stored in registers. if (VA.isRegLoc()) { EVT RegVT = VA.getLocVT(); @@ -3173,7 +3176,7 @@ ARMTargetLowering::LowerFormalArguments( assert(VA.isMemLoc()); assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); - int index = ArgLocs[i].getValNo(); + int index = VA.getValNo(); // Some Ins[] entries become multiple ArgLoc[] entries. // Process them only once. @@ -3186,6 +3189,8 @@ ARMTargetLowering::LowerFormalArguments( // Since they could be overwritten by lowering of arguments in case of // a tail call. if (Flags.isByVal()) { + assert(Ins[index].isOrigArg() && + "Byval arguments cannot be implicit"); unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed(); ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign()); Modified: head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon May 25 13:43:03 2015 (r283526) @@ -3667,43 +3667,44 @@ bool MipsAsmParser::parseDirectiveModule return false; } - if (Lexer.is(AsmToken::Identifier)) { - StringRef Option = Parser.getTok().getString(); - Parser.Lex(); + StringRef Option; + if (Parser.parseIdentifier(Option)) { + reportParseError("expected .module option identifier"); + return false; + } - if (Option == "oddspreg") { - getTargetStreamer().emitDirectiveModuleOddSPReg(true, isABI_O32()); - clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); - - if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token, expected end of statement"); - return false; - } + if (Option == "oddspreg") { + getTargetStreamer().emitDirectiveModuleOddSPReg(true, isABI_O32()); + clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); return false; - } else if (Option == "nooddspreg") { - if (!isABI_O32()) { - Error(L, "'.module nooddspreg' requires the O32 ABI"); - return false; - } + } - getTargetStreamer().emitDirectiveModuleOddSPReg(false, isABI_O32()); - setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); + return false; // parseDirectiveModule has finished successfully. + } else if (Option == "nooddspreg") { + if (!isABI_O32()) { + Error(L, "'.module nooddspreg' requires the O32 ABI"); + return false; + } - if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token, expected end of statement"); - return false; - } + getTargetStreamer().emitDirectiveModuleOddSPReg(false, isABI_O32()); + setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); return false; - } else if (Option == "fp") { - return parseDirectiveModuleFP(); } + return false; // parseDirectiveModule has finished successfully. + } else if (Option == "fp") { + return parseDirectiveModuleFP(); + } else { return Error(L, "'" + Twine(Option) + "' is not a valid .module option."); } - - return false; } /// parseDirectiveModuleFP Modified: head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Mon May 25 13:43:03 2015 (r283526) @@ -259,6 +259,11 @@ static DecodeStatus DecodeCacheOp(MCInst uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCacheOpR6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -304,6 +309,10 @@ static DecodeStatus DecodeFMem3(MCInst & uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1118,6 +1127,23 @@ static DecodeStatus DecodeCacheOpMM(MCIn return MCDisassembler::Success; } +static DecodeStatus DecodeCacheOpR6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = fieldFromInstruction(Insn, 7, 9); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::CreateImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1354,6 +1380,23 @@ static DecodeStatus DecodeFMem3(MCInst & return MCDisassembler::Success; } +static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<11>(Insn & 0x07ff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, Modified: head/contrib/llvm/lib/Target/Mips/Mips.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips.td Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/Mips.td Mon May 25 13:43:03 2015 (r283526) @@ -58,15 +58,15 @@ def MipsInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", - "Disable SVR4-style position-independent code.">; + "Disable SVR4-style position-independent code">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", - "General Purpose Registers are 64-bit wide.">; + "General Purpose Registers are 64-bit wide">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", - "Support 64-bit FP registers.">; + "Support 64-bit FP registers">; def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true", - "Support for FPXX.">; + "Support for FPXX">; def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true", - "IEEE 754-2008 NaN encoding.">; + "IEEE 754-2008 NaN encoding">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()", @@ -81,7 +81,7 @@ def FeatureNoOddSPReg : SubtargetFeatur "Disable odd numbered single-precision " "registers">; def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", - "true", "Enable vector FPU instructions.">; + "true", "Enable vector FPU instructions">; def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", "Mips I ISA Support [highly experimental]">; def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", Modified: head/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp Mon May 25 13:43:03 2015 (r283526) @@ -293,6 +293,9 @@ void Mips16InstrInfo::adjustStackPtrBigU void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { + if (Amount == 0) + return; + if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> BuildAddiuSpImm(MBB, I, Amount); else Modified: head/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td Mon May 25 13:43:03 2015 (r283526) @@ -379,7 +379,6 @@ class JMP_IDX_COMPACT_DESC_BASE<string o list<dag> Pattern = []; bit isTerminator = 1; bit hasDelaySlot = 0; - string DecoderMethod = "DecodeSimm16"; } class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, @@ -550,6 +549,7 @@ class CACHE_HINT_DESC<string instr_asm, dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); list<dag> Pattern = []; + string DecoderMethod = "DecodeCacheOpR6"; } class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; @@ -561,6 +561,7 @@ class COP2LD_DESC_BASE<string instr_asm, string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list<dag> Pattern = []; bit mayLoad = 1; + string DecoderMethod = "DecodeFMemCop2R6"; } class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; @@ -572,6 +573,7 @@ class COP2ST_DESC_BASE<string instr_asm, string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list<dag> Pattern = []; bit mayStore = 1; + string DecoderMethod = "DecodeFMemCop2R6"; } class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; Modified: head/contrib/llvm/lib/Target/Mips/MipsCCState.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/MipsCCState.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/MipsCCState.cpp Mon May 25 13:43:03 2015 (r283526) @@ -132,8 +132,8 @@ void MipsCCState::PreAnalyzeFormalArgume continue; } - assert(Ins[i].OrigArgIndex < MF.getFunction()->arg_size()); - std::advance(FuncArg, Ins[i].OrigArgIndex); + assert(Ins[i].getOrigArgIndex() < MF.getFunction()->arg_size()); + std::advance(FuncArg, Ins[i].getOrigArgIndex()); OriginalArgWasF128.push_back( originalTypeIsF128(FuncArg->getType(), nullptr)); Modified: head/contrib/llvm/lib/Target/Mips/MipsCallingConv.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/MipsCallingConv.td Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/MipsCallingConv.td Mon May 25 13:43:03 2015 (r283526) @@ -123,7 +123,7 @@ def CC_MipsN_SoftFloat : CallingConv<[ ]>; def CC_MipsN : CallingConv<[ - CCIfType<[i8, i16, i32], + CCIfType<[i8, i16, i32, i64], CCIfSubtargetNot<"isLittle()", CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, @@ -159,6 +159,10 @@ def CC_MipsN : CallingConv<[ // N32/64 variable arguments. // All arguments are passed in integer registers. def CC_MipsN_VarArg : CallingConv<[ + CCIfType<[i8, i16, i32, i64], + CCIfSubtargetNot<"isLittle()", + CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, + // All integers are promoted to 64-bit. CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, Modified: head/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp Mon May 25 13:43:03 2015 (r283526) @@ -619,6 +619,33 @@ static SDValue performSELECTCombine(SDNo return SDValue(); } +static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const MipsSubtarget &Subtarget) { + if (DCI.isBeforeLegalizeOps()) + return SDValue(); + + SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); + + ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); + if (!FalseC || FalseC->getZExtValue()) + return SDValue(); + + // Since RHS (False) is 0, we swap the order of the True/False operands + // (obviously also inverting the condition) so that we can + // take advantage of conditional moves using the $0 register. + // Example: + // return (a != 0) ? x : 0; + // load $reg, x + // movz $reg, $0, a + unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : + MipsISD::CMovFP_T; + + SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); + return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), + ValueIfFalse, FCC, ValueIfTrue, Glue); +} + static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) { @@ -752,6 +779,9 @@ SDValue MipsTargetLowering::PerformDAGC return performDivRemCombine(N, DAG, DCI, Subtarget); case ISD::SELECT: return performSELECTCombine(N, DAG, DCI, Subtarget); + case MipsISD::CMovFP_F: + case MipsISD::CMovFP_T: + return performCMovFPCombine(N, DAG, DCI, Subtarget); case ISD::AND: return performANDCombine(N, DAG, DCI, Subtarget); case ISD::OR: @@ -2039,7 +2069,7 @@ SDValue MipsTargetLowering::lowerShiftLe SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, - DAG.getConstant(0x20, MVT::i32)); + DAG.getConstant(VT.getSizeInBits(), MVT::i32)); Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, VT), ShiftLeftLo); Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); @@ -2078,11 +2108,12 @@ SDValue MipsTargetLowering::lowerShiftRi SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt); SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, - DAG.getConstant(0x20, MVT::i32)); - SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT)); + DAG.getConstant(VT.getSizeInBits(), MVT::i32)); + SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, + DAG.getConstant(VT.getSizeInBits() - 1, VT)); Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, - IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi); + IsSRA ? Ext : DAG.getConstant(0, VT), ShiftRightHi); SDValue Ops[2] = {Lo, Hi}; return DAG.getMergeValues(Ops, DL); @@ -2902,13 +2933,16 @@ MipsTargetLowering::LowerFormalArguments for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); - CurArgIdx = Ins[i].OrigArgIndex; + if (Ins[i].isOrigArg()) { + std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + } EVT ValVT = VA.getValVT(); ISD::ArgFlagsTy Flags = Ins[i].Flags; bool IsRegLoc = VA.isRegLoc(); if (Flags.isByVal()) { + assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); unsigned FirstByValReg, LastByValReg; unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); @@ -3029,6 +3063,15 @@ MipsTargetLowering::CanLowerReturn(Calli return CCInfo.CheckReturn(Outs, RetCC_Mips); } +bool +MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) { + if (Type == MVT::i32) + return true; + } + return IsSigned; +} + SDValue MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, Modified: head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h ============================================================================== --- head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h Mon May 25 13:43:03 2015 (r283526) @@ -472,6 +472,8 @@ namespace llvm { const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const override; + bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; + // Inline asm support ConstraintType getConstraintType(const std::string &Constraint) const override; Modified: head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Mon May 25 11:56:57 2015 (r283525) +++ head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Mon May 25 13:43:03 2015 (r283526) @@ -458,42 +458,42 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, - MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6; + MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, - MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6; + MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; let AdditionalPredicates = [NoNaNsFPMath] in { def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, - MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6; + MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, - MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6; + MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; } def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; + MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; + MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; let AdditionalPredicates = [NoNaNsFPMath] in { def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; + MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; + MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; } -let isCodeGenOnly=1 in { +let DecoderNamespace = "Mips64" in { def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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