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Date:      Wed, 23 Sep 2020 01:49:37 +0000 (UTC)
From:      Brandon Bergren <bdragon@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r366049 - head/sys/powerpc/powernv
Message-ID:  <202009230149.08N1nbXP078877@repo.freebsd.org>
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Author: bdragon
Date: Wed Sep 23 01:49:37 2020
New Revision: 366049
URL: https://svnweb.freebsd.org/changeset/base/366049

Log:
  [PowerPC64LE] Get XIVE up and running.
  
  More endian conversion.
  
  * Install TCEs correctly (i.e. in big endian)
  
  * Convert to big endian and back when setting up queue pages and IRQs.
  
  Sponsored by:	Tag1 Consulting, Inc.

Modified:
  head/sys/powerpc/powernv/opal_pci.c
  head/sys/powerpc/powernv/xive.c

Modified: head/sys/powerpc/powernv/opal_pci.c
==============================================================================
--- head/sys/powerpc/powernv/opal_pci.c	Wed Sep 23 01:41:51 2020	(r366048)
+++ head/sys/powerpc/powernv/opal_pci.c	Wed Sep 23 01:49:37 2020	(r366049)
@@ -385,7 +385,7 @@ opalpci_attach(device_t dev)
 		    (uintmax_t)sc->phb_id);
 
 	for (i = 0; i < entries; i++)
-		sc->tce[i] = (i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W;
+		sc->tce[i] = htobe64((i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W);
 
 	/* Map TCE for every PE. It seems necessary for Power8 */
 	for (i = 0; i < npe; i++) {

Modified: head/sys/powerpc/powernv/xive.c
==============================================================================
--- head/sys/powerpc/powernv/xive.c	Wed Sep 23 01:41:51 2020	(r366048)
+++ head/sys/powerpc/powernv/xive.c	Wed Sep 23 01:49:37 2020	(r366049)
@@ -377,6 +377,9 @@ xive_attach(device_t dev)
 		opal_call(OPAL_XIVE_GET_VP_INFO, xive_cpud->vp, NULL,
 		    vtophys(&xive_cpud->cam), NULL, vtophys(&xive_cpud->chip));
 
+		xive_cpud->cam = be64toh(xive_cpud->cam);
+		xive_cpud->chip = be64toh(xive_cpud->chip);
+
 		/* Allocate the queue page and populate the queue state data. */
 		xive_cpud->queue.q_page = contigmalloc(PAGE_SIZE, M_XIVE,
 		    M_ZERO | M_WAITOK, 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0);
@@ -707,6 +710,12 @@ xive_init_irq(struct xive_irq *irqd, u_int irq)
 	    vtophys(&trig_phys), vtophys(&esb_shift),
 	    vtophys(&irqd->chip));
 
+	irqd->flags = be64toh(irqd->flags);
+	eoi_phys = be64toh(eoi_phys);
+	trig_phys = be64toh(trig_phys);
+	esb_shift = be32toh(esb_shift);
+	irqd->chip = be32toh(irqd->chip);
+
 	irqd->girq = irq;
 	irqd->esb_size = 1 << esb_shift;
 	irqd->eoi_page = (vm_offset_t)pmap_mapdev(eoi_phys, irqd->esb_size);
@@ -721,6 +730,10 @@ xive_init_irq(struct xive_irq *irqd, u_int irq)
 
 	opal_call(OPAL_XIVE_GET_IRQ_CONFIG, irq, vtophys(&irqd->vp),
 	    vtophys(&irqd->prio), vtophys(&irqd->lirq));
+
+	irqd->vp = be64toh(irqd->vp);
+	irqd->prio = be64toh(irqd->prio);
+	irqd->lirq = be32toh(irqd->lirq);
 }
 
 /* Allocate an IRQ struct before populating it. */

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