Date: Sun, 5 Oct 2014 21:32:04 -0300 From: Martin Galvan <omgalvan.86@gmail.com> To: Warner Losh <imp@bsdimp.com> Cc: freebsd-drivers@freebsd.org, freebsd-embedded@freebsd.org Subject: Re: A few questions about SD/MMC drivers Message-ID: <CAN19L9FudV6PtsmE359Wfb216am3eaiEJtd6ixq2eOfJDZHbkA@mail.gmail.com> In-Reply-To: <FEB6A362-40F7-4418-8B28-F03506F6C365@bsdimp.com> References: <CAN19L9ENsuAR6_aXwJSRdfDz6UgE6kU%2BrCkGGsdK7tRcUes%2B0w@mail.gmail.com> <FEB6A362-40F7-4418-8B28-F03506F6C365@bsdimp.com>
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Hi Warner! Thanks for your answer. 2014-10-05 20:06 GMT-03:00 Warner Losh <imp@bsdimp.com>: > On Oct 5, 2014, at 4:05 PM, Martin Galvan <omgalvan.86@gmail.com> wrote: > >> 2) The code I'm working on is based off the Linux driver for the same >> host, which as of today stands as the only "documentation", so to >> speak, on that particular host. According to the Linux driver, we need >> to do a phase shift adjustment while setting the clock in the set_ios >> function. That involves several steps, one of which is calling >> clk_set_rate, which seems to be a function many other Linux drivers >> use. As I'm not familiar with Linux kernel internals, so far I haven't >> been able to find the equivalent for that function on BSD, so how >> should I go about this? > > Most likely you=E2=80=99ll need to write the clock infrastructure for all= winner to > make this work. I don=E2=80=99t believe that it is actually there today. = Note: I=E2=80=99ve > not looked at the allwinner core code in a long time, so maybe this > has already been rectified. Well, there's a a10_clk.c file in the current tree that (sort of) takes care of the clocking for Allwinner. > clk_set_rate in Linux adjusts the produced clock frequency for a clock > that=E2=80=99s programmable in the SoC. I actually forgot to mention I'm reworking Alex Fedorov's MMC patch. While indeed there's not a function for clocking the MMC host yet in the tree, Alex's patch did include a basic clocking function in a10_clk.c that does the necessary register magic to get things working, but doesn't do any of the phase shifting. I believe I can get that done if I could find a way to implement something similar to clk_set_rate, at least for this driver. In any case, the phase shift thing seems to be mostly for speeding things up a bit (I managed to get Alex's driver working by fixing a couple of bugs here and there; it's kind of slow since it doesn't support DMA nor multiblock operations yet), and we can probably add that later. Speaking of multiblock support, I noticed at some point your at91_mci.c had multiblock operations working but then you switched to single-block only (at least I'm sure I saw a version where MMCBR_IVAR_MAX_DATA returned something other than 1). Do you remember what happened there? Again, thanks a lot for your answer.
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