Date: Fri, 8 Mar 2024 08:19:28 GMT From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: fc31d474c40a - stable/14 - Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks): Message-ID: <202403080819.4288JSd7061594@gitrepo.freebsd.org>
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The branch stable/14 has been updated by dim: URL: https://cgit.FreeBSD.org/src/commit/?id=fc31d474c40a50066310b3d03a8eb0724a00609d commit fc31d474c40a50066310b3d03a8eb0724a00609d Author: Dimitry Andric <dim@FreeBSD.org> AuthorDate: 2024-03-04 20:30:54 +0000 Commit: Dimitry Andric <dim@FreeBSD.org> CommitDate: 2024-03-08 08:15:49 +0000 Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks): [PEI] Don't zero out noreg operands A tail call may have $noreg operands. Fixes a crash. Reviewed By: xgupta Differential Revision: https://reviews.llvm.org/D156485 This should fix an assertion failure building qemu, specifically those parts using -fzero-call-used-regs. Reported by: Daniel Berrangé <dan-freebsd@berrange.com> PR: 277474 MFC after: 3 days (cherry picked from commit a39b3aa463f3474fabb3aedb5aecf943b54b4357) --- contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp index e323aaaeefaf..49047719fdaa 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1285,6 +1285,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; MCRegister Reg = MO.getReg(); + if (!Reg) + continue; // This picks up sibling registers (e.q. %al -> %ah). for (MCRegUnit Unit : TRI.regunits(Reg)) @@ -1308,8 +1310,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { if (!MO.isReg()) continue; - for (const MCPhysReg &Reg : - TRI.sub_and_superregs_inclusive(MO.getReg())) + MCRegister Reg = MO.getReg(); + if (!Reg) + continue; + + for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg)) RegsToZero.reset(Reg); } }
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