Date: Sat, 31 Oct 2015 00:04:44 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290218 - head/sys/mips/include Message-ID: <201510310004.t9V04iU0016792@repo.freebsd.org>
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Author: adrian Date: Sat Oct 31 00:04:44 2015 New Revision: 290218 URL: https://svnweb.freebsd.org/changeset/base/290218 Log: mips74k: use cache-writeback for memory, not writethrough. When I ported this code from netbsd I was .. slightly mips74k greener. I used writethrough because (a) it's what netbsd did, and (b) if I used writethrough then things "didn't work." Fast-forward a couple years, more MIPS hacking and a whole lot more understanding of the bus APIs (the last few commits notwithstanding; it's been a long week, ok?) and I have this working for arge, argemdio, spi and ath. Hans has it working for USB. The ath barrier code will come in a later commit. This gets the routing throughput up from 220mbit -> 337mbit. I'm sure the bridging throughput will be similarly improved. Tested: * QCA955x SoC, routing workload. Modified: head/sys/mips/include/cpuregs.h Modified: head/sys/mips/include/cpuregs.h ============================================================================== --- head/sys/mips/include/cpuregs.h Fri Oct 30 23:59:52 2015 (r290217) +++ head/sys/mips/include/cpuregs.h Sat Oct 31 00:04:44 2015 (r290218) @@ -151,7 +151,7 @@ #if defined(CPU_MIPS74KC) #define MIPS_CCA_UNCACHED 0x02 -#define MIPS_CCA_CACHED 0x00 +#define MIPS_CCA_CACHED 0x03 #endif #ifndef MIPS_CCA_UNCACHED
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