Date: Thu, 9 Jun 2005 12:26:20 +0000 (UTC) From: Olivier Houchard <cognet@FreeBSD.org> To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/arm/arm intr.c nexus.c src/sys/arm/include intr.h src/sys/arm/sa11x0 sa11x0_irqhandler.c src/sys/arm/xscale/i80321 i80321.c i80321_pci.c iq80321.c Message-ID: <200506091226.j59CQKwE022917@repoman.freebsd.org>
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cognet 2005-06-09 12:26:20 UTC
FreeBSD src repository
Modified files:
sys/arm/arm intr.c nexus.c
sys/arm/include intr.h
sys/arm/sa11x0 sa11x0_irqhandler.c
sys/arm/xscale/i80321 i80321.c i80321_pci.c iq80321.c
Log:
- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32
interrupts.
- Implement teardown methods where appropriate.
Revision Changes Path
1.9 +14 -39 src/sys/arm/arm/intr.c
1.5 +13 -0 src/sys/arm/arm/nexus.c
1.5 +4 -4 src/sys/arm/include/intr.h
1.4 +14 -16 src/sys/arm/sa11x0/sa11x0_irqhandler.c
1.5 +5 -4 src/sys/arm/xscale/i80321/i80321.c
1.4 +9 -1 src/sys/arm/xscale/i80321/i80321_pci.c
1.8 +14 -4 src/sys/arm/xscale/i80321/iq80321.c
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