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Date:      Fri, 3 Jan 2020 20:28:07 +0000 (UTC)
From:      Dimitry Andric <dim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r356332 - head/contrib/llvm-project/llvm/lib/Target/RISCV
Message-ID:  <202001032028.003KS7Qf002366@repo.freebsd.org>
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Author: dim
Date: Fri Jan  3 20:28:06 2020
New Revision: 356332
URL: https://svnweb.freebsd.org/changeset/base/356332

Log:
  Merge commit d7be3eab5 from llvm git (by Luís Marques):
  
    [RISCV] Handle fcopysign(f32, f64) and fcopysign(f64, f32)
  
    Summary: Adds tablegen patterns to explicitly handle fcopysign where
    the magnitude and sign arguments have different types, due to the
    sign value casts being removed the by DAGCombiner. Support for RV32IF
    follows in a separate commit. Adds tests for all relevant scenarios
    except RV32IF.
  
    Reviewers: lenary
    Reviewed By: lenary
    Tags: #llvm
    Differential Revision: https://reviews.llvm.org/D70678
  
  This is a prerequisite for building and linking hard- and soft-float
  riscv worlds with clang and lld.
  
  Requested by:	jhb
  MFC after:	1 week
  X-MFC-With:	r353358

Modified:
  head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Modified: head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
==============================================================================
--- head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td	Fri Jan  3 20:19:17 2020	(r356331)
+++ head/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoD.td	Fri Jan  3 20:28:06 2020	(r356332)
@@ -231,6 +231,9 @@ def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 
 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
+def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
+def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
+                                                              0b111))>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),

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