Date: Thu, 19 May 2011 17:18:13 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r222098 - stable/8/sys/dev/mii Message-ID: <201105191718.p4JHIDgT046367@svn.freebsd.org>
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Author: yongari Date: Thu May 19 17:18:13 2011 New Revision: 222098 URL: http://svn.freebsd.org/changeset/base/222098 Log: MFC r221817: Explicitly clear 1000baseT control register for F1 PHY used in AR8132 FastEthernet controller. The PHY has no ability to establish a gigabit link. Previously only link parters which support down-shifting was able to establish link. This change should fix a long standing link establishment issue of AR8132. PR: kern/156935 Modified: stable/8/sys/dev/mii/atphy.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) Modified: stable/8/sys/dev/mii/atphy.c ============================================================================== --- stable/8/sys/dev/mii/atphy.c Thu May 19 15:18:35 2011 (r222097) +++ stable/8/sys/dev/mii/atphy.c Thu May 19 17:18:13 2011 (r222098) @@ -384,6 +384,7 @@ atphy_anar(struct ifmedia_entry *ife) static int atphy_setmedia(struct mii_softc *sc, int media) { + struct atphy_softc *asc; uint16_t anar; anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; @@ -396,6 +397,20 @@ atphy_setmedia(struct mii_softc *sc, int (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); + else { + /* + * AR8132 has 10/100 PHY and the PHY uses the same + * model number of F1 gigabit PHY. The PHY has no + * ability to establish gigabit link so explicitly + * disable 1000baseT configuration for the PHY. + * Otherwise, there is a case that atphy(4) could + * not establish a link against gigabit link partner + * unless the link partner supports down-shifting. + */ + asc = (struct atphy_softc *)sc; + if (asc->mii_model == MII_MODEL_ATHEROS_F1) + PHY_WRITE(sc, MII_100T2CR, 0); + } PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); return (EJUSTRETURN);
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