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Date:      Thu, 26 May 2016 00:03:23 +0000 (UTC)
From:      Ian Lepore <ian@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r300701 - in head/sys: arm/arm arm/include sys
Message-ID:  <201605260003.u4Q03NjC054902@repo.freebsd.org>

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Author: ian
Date: Thu May 26 00:03:23 2016
New Revision: 300701
URL: https://svnweb.freebsd.org/changeset/base/300701

Log:
  Disable alignment faults on armv6, adjust various alignment-related macros
  to match the new state of affairs.  The hardware we support has always been
  able to do unaligned accesses, we've just never enabled it until now.
  
  This brings FreeBSD into line with all the other major OSes, and should help
  with the growing volume of 3rd-party software that assumes unaligned access
  will just work on armv6 and armv7.

Modified:
  head/sys/arm/arm/locore-v6.S
  head/sys/arm/include/_align.h
  head/sys/arm/include/_types.h
  head/sys/arm/include/param.h
  head/sys/sys/param.h

Modified: head/sys/arm/arm/locore-v6.S
==============================================================================
--- head/sys/arm/arm/locore-v6.S	Wed May 25 23:06:52 2016	(r300700)
+++ head/sys/arm/arm/locore-v6.S	Thu May 26 00:03:23 2016	(r300701)
@@ -129,12 +129,12 @@ ASENTRY_NP(_start)
 	 */
 1:
 	bic	r7, #CPU_CONTROL_DC_ENABLE
+	bic	r7, #CPU_CONTROL_AFLT_ENABLE
 	bic	r7, #CPU_CONTROL_MMU_ENABLE
 	bic	r7, #CPU_CONTROL_IC_ENABLE
 	bic	r7, #CPU_CONTROL_BPRD_ENABLE
 	bic	r7, #CPU_CONTROL_SW_ENABLE
 	orr	r7, #CPU_CONTROL_UNAL_ENABLE
-	orr	r7, #CPU_CONTROL_AFLT_ENABLE
 	orr	r7, #CPU_CONTROL_VECRELOC
 	mcr	CP15_SCTLR(r7)
 	DSB
@@ -453,12 +453,12 @@ ASENTRY_NP(mpentry)
 	/* Setup core, disable all caches. */
 	mrc	CP15_SCTLR(r0)
 	bic	r0, #CPU_CONTROL_MMU_ENABLE
+	bic	r0, #CPU_CONTROL_AFLT_ENABLE
 	bic	r0, #CPU_CONTROL_DC_ENABLE
 	bic	r0, #CPU_CONTROL_IC_ENABLE
 	bic	r0, #CPU_CONTROL_BPRD_ENABLE
 	bic	r0, #CPU_CONTROL_SW_ENABLE
 	orr	r0, #CPU_CONTROL_UNAL_ENABLE
-	orr	r0, #CPU_CONTROL_AFLT_ENABLE
 	orr	r0, #CPU_CONTROL_VECRELOC
 	mcr	CP15_SCTLR(r0)
 	DSB

Modified: head/sys/arm/include/_align.h
==============================================================================
--- head/sys/arm/include/_align.h	Wed May 25 23:06:52 2016	(r300700)
+++ head/sys/arm/include/_align.h	Thu May 26 00:03:23 2016	(r300701)
@@ -46,7 +46,11 @@
  * is sufficient for any data type, pointer or numeric.  The resulting type
  * is equivelent to arm's uintptr_t (but is purposely spelled "unsigned" here).
  */
+#if __ARM_ARCH >= 6
+#define	_ALIGNBYTES	(sizeof(int) - 1)
+#else
 #define	_ALIGNBYTES	(sizeof(long long) - 1)
+#endif
 #define	_ALIGN(p)	(((unsigned)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
 
 #endif /* !_ARM_INCLUDE__ALIGN_H_ */

Modified: head/sys/arm/include/_types.h
==============================================================================
--- head/sys/arm/include/_types.h	Wed May 25 23:06:52 2016	(r300700)
+++ head/sys/arm/include/_types.h	Thu May 26 00:03:23 2016	(r300701)
@@ -43,6 +43,10 @@
 #error this file needs sys/cdefs.h as a prerequisite
 #endif
 
+#if __ARM_ARCH >= 6
+#define __NO_STRICT_ALIGNMENT
+#endif
+
 /*
  * Basic types upon which most other types are built.
  */

Modified: head/sys/arm/include/param.h
==============================================================================
--- head/sys/arm/include/param.h	Wed May 25 23:06:52 2016	(r300700)
+++ head/sys/arm/include/param.h	Thu May 26 00:03:23 2016	(r300701)
@@ -90,8 +90,16 @@
  * is valid to fetch data elements of type t from on this architecture.
  * This does not reflect the optimal alignment, just the possibility
  * (within reasonable limits).
+ *
+ * armv4 and v5 require alignment to the type's size.  armv6 and later require
+ * that an 8-byte type be aligned to at least a 4-byte boundary; access to
+ * smaller types can be unaligned.
  */
+#if __ARM_ARCH >= 6
+#define	ALIGNED_POINTER(p, t)	(((sizeof(t) != 8) || ((unsigned)(p) & 3) == 0))
+#else
 #define	ALIGNED_POINTER(p, t)	((((unsigned)(p)) & (sizeof(t)-1)) == 0)
+#endif
 
 /*
  * CACHE_LINE_SIZE is the compile-time maximum cache line size for an

Modified: head/sys/sys/param.h
==============================================================================
--- head/sys/sys/param.h	Wed May 25 23:06:52 2016	(r300700)
+++ head/sys/sys/param.h	Thu May 26 00:03:23 2016	(r300701)
@@ -58,7 +58,7 @@
  *		in the range 5 to 9.
  */
 #undef __FreeBSD_version
-#define __FreeBSD_version 1100112	/* Master, propagated to newvers */
+#define __FreeBSD_version 1100113	/* Master, propagated to newvers */
 
 /*
  * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,



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