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Date:      Thu, 29 Nov 2018 06:43:24 +0000 (UTC)
From:      Andrew Rybchenko <arybchik@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r341193 - head/sys/dev/sfxge/common
Message-ID:  <201811290643.wAT6hODt024995@repo.freebsd.org>

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Author: arybchik
Date: Thu Nov 29 06:43:23 2018
New Revision: 341193
URL: https://svnweb.freebsd.org/changeset/base/341193

Log:
  sfxge(4): update MCDI headers
  
  Sponsored by:   Solarflare Communications, Inc.
  Differential Revision:  https://reviews.freebsd.org/D18224

Modified:
  head/sys/dev/sfxge/common/efx_regs_mcdi.h
  head/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h

Modified: head/sys/dev/sfxge/common/efx_regs_mcdi.h
==============================================================================
--- head/sys/dev/sfxge/common/efx_regs_mcdi.h	Thu Nov 29 06:43:12 2018	(r341192)
+++ head/sys/dev/sfxge/common/efx_regs_mcdi.h	Thu Nov 29 06:43:23 2018	(r341193)
@@ -301,7 +301,8 @@
 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
 /* Workaround 26807 could not be turned on/off because some functions
  * have already installed filters. See the comment at
- * MC_CMD_WORKAROUND_BUG26807. */
+ * MC_CMD_WORKAROUND_BUG26807.
+ * May also returned for other operations such as sub-variant switching. */
 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
 /* The clock whose frequency you've attempted to set set
  * doesn't exist on this NIC */
@@ -320,6 +321,10 @@
  * away.  This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
  * datapath absence may be temporary*/
 #define MC_CMD_ERR_NO_DATAPATH 0x1019
+/* The operation could not complete because some VIs are allocated */
+#define MC_CMD_ERR_VIS_PRESENT 0x101a
+/* The operation could not complete because some PIO buffers are allocated */
+#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
 
 #define MC_CMD_ERR_CODE_OFST 0
 
@@ -404,7 +409,7 @@
 #define	MCDI_EVENT_LEVEL_LBN 33
 #define	MCDI_EVENT_LEVEL_WIDTH 3
 /* enum: Info. */
-#define	MCDI_EVENT_LEVEL_INFO  0x0
+#define	MCDI_EVENT_LEVEL_INFO 0x0
 /* enum: Warning. */
 #define	MCDI_EVENT_LEVEL_WARN 0x1
 /* enum: Error. */
@@ -424,21 +429,21 @@
 #define	MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
 #define	MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
 /* enum: Link is down or link speed could not be determined */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN  0x0
+#define	MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
 /* enum: 100Mbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_100M  0x1
+#define	MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
 /* enum: 1Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_1G  0x2
+#define	MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
 /* enum: 10Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_10G  0x3
+#define	MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
 /* enum: 40Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_40G  0x4
+#define	MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
 /* enum: 25Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_25G  0x5
+#define	MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
 /* enum: 50Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_50G  0x6
+#define	MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
 /* enum: 100Gbs */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_100G  0x7
+#define	MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
 #define	MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
 #define	MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
@@ -645,23 +650,23 @@
 /* enum: Transmit error */
 #define	MCDI_EVENT_CODE_TX_ERR 0xb
 /* enum: Tx flush has completed */
-#define	MCDI_EVENT_CODE_TX_FLUSH  0xc
+#define	MCDI_EVENT_CODE_TX_FLUSH 0xc
 /* enum: PTP packet received timestamp */
-#define	MCDI_EVENT_CODE_PTP_RX  0xd
+#define	MCDI_EVENT_CODE_PTP_RX 0xd
 /* enum: PTP NIC failure */
-#define	MCDI_EVENT_CODE_PTP_FAULT  0xe
+#define	MCDI_EVENT_CODE_PTP_FAULT 0xe
 /* enum: PTP PPS event */
-#define	MCDI_EVENT_CODE_PTP_PPS  0xf
+#define	MCDI_EVENT_CODE_PTP_PPS 0xf
 /* enum: Rx flush has completed */
-#define	MCDI_EVENT_CODE_RX_FLUSH  0x10
+#define	MCDI_EVENT_CODE_RX_FLUSH 0x10
 /* enum: Receive error */
 #define	MCDI_EVENT_CODE_RX_ERR 0x11
 /* enum: AOE fault */
-#define	MCDI_EVENT_CODE_AOE  0x12
+#define	MCDI_EVENT_CODE_AOE 0x12
 /* enum: Network port calibration failed (VCAL). */
-#define	MCDI_EVENT_CODE_VCAL_FAIL  0x13
+#define	MCDI_EVENT_CODE_VCAL_FAIL 0x13
 /* enum: HW PPS event */
-#define	MCDI_EVENT_CODE_HW_PPS  0x14
+#define	MCDI_EVENT_CODE_HW_PPS 0x14
 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
  * a different format)
  */
@@ -693,7 +698,7 @@
 /* enum: Artificial event generated by host and posted via MC for test
  * purposes.
  */
-#define	MCDI_EVENT_CODE_TESTGEN  0xfa
+#define	MCDI_EVENT_CODE_TESTGEN 0xfa
 #define	MCDI_EVENT_CMDDONE_DATA_OFST 0
 #define	MCDI_EVENT_CMDDONE_DATA_LEN 4
 #define	MCDI_EVENT_CMDDONE_DATA_LBN 0
@@ -823,7 +828,7 @@
 #define	FCDI_EVENT_LEVEL_LBN 33
 #define	FCDI_EVENT_LEVEL_WIDTH 3
 /* enum: Info. */
-#define	FCDI_EVENT_LEVEL_INFO  0x0
+#define	FCDI_EVENT_LEVEL_INFO 0x0
 /* enum: Warning. */
 #define	FCDI_EVENT_LEVEL_WARN 0x1
 /* enum: Error. */
@@ -955,7 +960,7 @@
 #define	MUM_EVENT_LEVEL_LBN 33
 #define	MUM_EVENT_LEVEL_WIDTH 3
 /* enum: Info. */
-#define	MUM_EVENT_LEVEL_INFO  0x0
+#define	MUM_EVENT_LEVEL_INFO 0x0
 /* enum: Warning. */
 #define	MUM_EVENT_LEVEL_WARN 0x1
 /* enum: Error. */
@@ -1100,7 +1105,7 @@
 #define	MC_CMD_COPYCODE 0x3
 #undef	MC_CMD_0x3_PRIVILEGE_CTG
 
-#define	MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
 
 /* MC_CMD_COPYCODE_IN msgrequest */
 #define	MC_CMD_COPYCODE_IN_LEN 16
@@ -1187,7 +1192,7 @@
 #define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
 #define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
 /* enum: indicates that the MC wasn't flash booted */
-#define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL  0xdeadbeef
+#define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
@@ -1607,11 +1612,10 @@
 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
 
-/* MC_CMD_PTP_IN_RESET_STATS msgrequest */
+/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
 #define	MC_CMD_PTP_IN_RESET_STATS_LEN 8
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
-/* Reset PTP statistics */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
 
@@ -1762,11 +1766,10 @@
 /* enum: External. */
 #define	MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
 
-/* MC_CMD_PTP_IN_RST_CLK msgrequest */
+/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
 #define	MC_CMD_PTP_IN_RST_CLK_LEN 8
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_CMD_LEN 4 */
-/* Reset value of Timer Reg. */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
 
@@ -2246,7 +2249,7 @@
 #define	MC_CMD_HP 0x54
 #undef	MC_CMD_0x54_PRIVILEGE_CTG
 
-#define	MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
 
 /* MC_CMD_HP_IN msgrequest */
 #define	MC_CMD_HP_IN_LEN 16
@@ -2589,28 +2592,51 @@
 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
 #define	MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
-/* See MC_CMD_CAPABILITIES */
+/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
+ * EF10 and later (use MC_CMD_GET_CAPABILITIES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
-/* See MC_CMD_CAPABILITIES */
+/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
+ * EF10 and later (use MC_CMD_GET_CAPABILITIES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
 #define	MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
+/* Base MAC address for Siena Port0. Unused on EF10 and later (use
+ * MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
+/* Base MAC address for Siena Port1. Unused on EF10 and later (use
+ * MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
+/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
+ * MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
+/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
+ * MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
+/* Increment between addresses in MAC address pool for Siena Port0. Unused on
+ * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
+/* Increment between addresses in MAC address pool for Siena Port1. Unused on
+ * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
+ */
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
 #define	MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
-/* This field contains a 16-bit value for each of the types of NVRAM area. The
- * values are defined in the firmware/mc/platform/.c file for a specific board
- * type, but otherwise have no meaning to the MC; they are used by the driver
- * to manage selection of appropriate firmware updates.
+/* Siena only. This field contains a 16-bit value for each of the types of
+ * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
+ * specific board type, but otherwise have no meaning to the MC; they are used
+ * by the driver to manage selection of appropriate firmware updates. Unused on
+ * EF10 and later (use MC_CMD_NVRAM_METADATA).
  */
 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
 #define	MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
@@ -2727,8 +2753,14 @@
 #define	MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
 #define	MC_CMD_DRV_ATTACH_LBN 0
 #define	MC_CMD_DRV_ATTACH_WIDTH 1
+#define	MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
+#define	MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
 #define	MC_CMD_DRV_PREBOOT_LBN 1
 #define	MC_CMD_DRV_PREBOOT_WIDTH 1
+#define	MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
+#define	MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
+#define	MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
+#define	MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
 /* 1 to set new state, or 0 to just report the existing state */
 #define	MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
 #define	MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
@@ -2753,8 +2785,12 @@
 #define	MC_CMD_FW_RULES_ENGINE 0x5
 /* enum: Prefer to use firmware with additional DPDK support */
 #define	MC_CMD_FW_DPDK 0x6
+/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
+ * bug69716)
+ */
+#define	MC_CMD_FW_L3XUDP 0x7
 /* enum: Only this option is allowed for non-admin functions */
-#define	MC_CMD_FW_DONT_CARE  0xffffffff
+#define	MC_CMD_FW_DONT_CARE 0xffffffff
 
 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
 #define	MC_CMD_DRV_ATTACH_OUT_LEN 4
@@ -3101,7 +3137,7 @@
 #define	MC_CMD_START_BIST 0x25
 #undef	MC_CMD_0x25_PRIVILEGE_CTG
 
-#define	MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
 
 /* MC_CMD_START_BIST_IN msgrequest */
 #define	MC_CMD_START_BIST_IN_LEN 4
@@ -3141,7 +3177,7 @@
 #define	MC_CMD_POLL_BIST 0x26
 #undef	MC_CMD_0x26_PRIVILEGE_CTG
 
-#define	MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
 
 /* MC_CMD_POLL_BIST_IN msgrequest */
 #define	MC_CMD_POLL_BIST_IN_LEN 0
@@ -3342,83 +3378,83 @@
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
 /* enum: None. */
-#define	MC_CMD_LOOPBACK_NONE  0x0
+#define	MC_CMD_LOOPBACK_NONE 0x0
 /* enum: Data. */
-#define	MC_CMD_LOOPBACK_DATA  0x1
+#define	MC_CMD_LOOPBACK_DATA 0x1
 /* enum: GMAC. */
-#define	MC_CMD_LOOPBACK_GMAC  0x2
+#define	MC_CMD_LOOPBACK_GMAC 0x2
 /* enum: XGMII. */
 #define	MC_CMD_LOOPBACK_XGMII 0x3
 /* enum: XGXS. */
-#define	MC_CMD_LOOPBACK_XGXS  0x4
+#define	MC_CMD_LOOPBACK_XGXS 0x4
 /* enum: XAUI. */
-#define	MC_CMD_LOOPBACK_XAUI  0x5
+#define	MC_CMD_LOOPBACK_XAUI 0x5
 /* enum: GMII. */
-#define	MC_CMD_LOOPBACK_GMII  0x6
+#define	MC_CMD_LOOPBACK_GMII 0x6
 /* enum: SGMII. */
-#define	MC_CMD_LOOPBACK_SGMII  0x7
+#define	MC_CMD_LOOPBACK_SGMII 0x7
 /* enum: XGBR. */
-#define	MC_CMD_LOOPBACK_XGBR  0x8
+#define	MC_CMD_LOOPBACK_XGBR 0x8
 /* enum: XFI. */
-#define	MC_CMD_LOOPBACK_XFI  0x9
+#define	MC_CMD_LOOPBACK_XFI 0x9
 /* enum: XAUI Far. */
-#define	MC_CMD_LOOPBACK_XAUI_FAR  0xa
+#define	MC_CMD_LOOPBACK_XAUI_FAR 0xa
 /* enum: GMII Far. */
-#define	MC_CMD_LOOPBACK_GMII_FAR  0xb
+#define	MC_CMD_LOOPBACK_GMII_FAR 0xb
 /* enum: SGMII Far. */
-#define	MC_CMD_LOOPBACK_SGMII_FAR  0xc
+#define	MC_CMD_LOOPBACK_SGMII_FAR 0xc
 /* enum: XFI Far. */
-#define	MC_CMD_LOOPBACK_XFI_FAR  0xd
+#define	MC_CMD_LOOPBACK_XFI_FAR 0xd
 /* enum: GPhy. */
-#define	MC_CMD_LOOPBACK_GPHY  0xe
+#define	MC_CMD_LOOPBACK_GPHY 0xe
 /* enum: PhyXS. */
-#define	MC_CMD_LOOPBACK_PHYXS  0xf
+#define	MC_CMD_LOOPBACK_PHYXS 0xf
 /* enum: PCS. */
-#define	MC_CMD_LOOPBACK_PCS  0x10
+#define	MC_CMD_LOOPBACK_PCS 0x10
 /* enum: PMA-PMD. */
-#define	MC_CMD_LOOPBACK_PMAPMD  0x11
+#define	MC_CMD_LOOPBACK_PMAPMD 0x11
 /* enum: Cross-Port. */
-#define	MC_CMD_LOOPBACK_XPORT  0x12
+#define	MC_CMD_LOOPBACK_XPORT 0x12
 /* enum: XGMII-Wireside. */
-#define	MC_CMD_LOOPBACK_XGMII_WS  0x13
+#define	MC_CMD_LOOPBACK_XGMII_WS 0x13
 /* enum: XAUI Wireside. */
-#define	MC_CMD_LOOPBACK_XAUI_WS  0x14
+#define	MC_CMD_LOOPBACK_XAUI_WS 0x14
 /* enum: XAUI Wireside Far. */
-#define	MC_CMD_LOOPBACK_XAUI_WS_FAR  0x15
+#define	MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
 /* enum: XAUI Wireside near. */
-#define	MC_CMD_LOOPBACK_XAUI_WS_NEAR  0x16
+#define	MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
 /* enum: GMII Wireside. */
-#define	MC_CMD_LOOPBACK_GMII_WS  0x17
+#define	MC_CMD_LOOPBACK_GMII_WS 0x17
 /* enum: XFI Wireside. */
-#define	MC_CMD_LOOPBACK_XFI_WS  0x18
+#define	MC_CMD_LOOPBACK_XFI_WS 0x18
 /* enum: XFI Wireside Far. */
-#define	MC_CMD_LOOPBACK_XFI_WS_FAR  0x19
+#define	MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
 /* enum: PhyXS Wireside. */
-#define	MC_CMD_LOOPBACK_PHYXS_WS  0x1a
+#define	MC_CMD_LOOPBACK_PHYXS_WS 0x1a
 /* enum: PMA lanes MAC-Serdes. */
-#define	MC_CMD_LOOPBACK_PMA_INT  0x1b
+#define	MC_CMD_LOOPBACK_PMA_INT 0x1b
 /* enum: KR Serdes Parallel (Encoder). */
-#define	MC_CMD_LOOPBACK_SD_NEAR  0x1c
+#define	MC_CMD_LOOPBACK_SD_NEAR 0x1c
 /* enum: KR Serdes Serial. */
-#define	MC_CMD_LOOPBACK_SD_FAR  0x1d
+#define	MC_CMD_LOOPBACK_SD_FAR 0x1d
 /* enum: PMA lanes MAC-Serdes Wireside. */
-#define	MC_CMD_LOOPBACK_PMA_INT_WS  0x1e
+#define	MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
 /* enum: KR Serdes Parallel Wireside (Full PCS). */
-#define	MC_CMD_LOOPBACK_SD_FEP2_WS  0x1f
+#define	MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
-#define	MC_CMD_LOOPBACK_SD_FEP1_5_WS  0x20
+#define	MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
-#define	MC_CMD_LOOPBACK_SD_FEP_WS  0x21
+#define	MC_CMD_LOOPBACK_SD_FEP_WS 0x21
 /* enum: KR Serdes Serial Wireside. */
-#define	MC_CMD_LOOPBACK_SD_FES_WS  0x22
+#define	MC_CMD_LOOPBACK_SD_FES_WS 0x22
 /* enum: Near side of AOE Siena side port */
-#define	MC_CMD_LOOPBACK_AOE_INT_NEAR  0x23
+#define	MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
 /* enum: Medford Wireside datapath loopback */
-#define	MC_CMD_LOOPBACK_DATA_WS  0x24
+#define	MC_CMD_LOOPBACK_DATA_WS 0x24
 /* enum: Force link up without setting up any physical loopback (snapper use
  * only)
  */
-#define	MC_CMD_LOOPBACK_FORCE_EXT_LINK  0x25
+#define	MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
 /* Supported loopbacks. */
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
@@ -3458,83 +3494,83 @@
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
 /* enum: None. */
-/*               MC_CMD_LOOPBACK_NONE  0x0 */
+/*               MC_CMD_LOOPBACK_NONE 0x0 */
 /* enum: Data. */
-/*               MC_CMD_LOOPBACK_DATA  0x1 */
+/*               MC_CMD_LOOPBACK_DATA 0x1 */
 /* enum: GMAC. */
-/*               MC_CMD_LOOPBACK_GMAC  0x2 */
+/*               MC_CMD_LOOPBACK_GMAC 0x2 */
 /* enum: XGMII. */
 /*               MC_CMD_LOOPBACK_XGMII 0x3 */
 /* enum: XGXS. */
-/*               MC_CMD_LOOPBACK_XGXS  0x4 */
+/*               MC_CMD_LOOPBACK_XGXS 0x4 */
 /* enum: XAUI. */
-/*               MC_CMD_LOOPBACK_XAUI  0x5 */
+/*               MC_CMD_LOOPBACK_XAUI 0x5 */
 /* enum: GMII. */
-/*               MC_CMD_LOOPBACK_GMII  0x6 */
+/*               MC_CMD_LOOPBACK_GMII 0x6 */
 /* enum: SGMII. */
-/*               MC_CMD_LOOPBACK_SGMII  0x7 */
+/*               MC_CMD_LOOPBACK_SGMII 0x7 */
 /* enum: XGBR. */
-/*               MC_CMD_LOOPBACK_XGBR  0x8 */
+/*               MC_CMD_LOOPBACK_XGBR 0x8 */
 /* enum: XFI. */
-/*               MC_CMD_LOOPBACK_XFI  0x9 */
+/*               MC_CMD_LOOPBACK_XFI 0x9 */
 /* enum: XAUI Far. */
-/*               MC_CMD_LOOPBACK_XAUI_FAR  0xa */
+/*               MC_CMD_LOOPBACK_XAUI_FAR 0xa */
 /* enum: GMII Far. */
-/*               MC_CMD_LOOPBACK_GMII_FAR  0xb */
+/*               MC_CMD_LOOPBACK_GMII_FAR 0xb */
 /* enum: SGMII Far. */
-/*               MC_CMD_LOOPBACK_SGMII_FAR  0xc */
+/*               MC_CMD_LOOPBACK_SGMII_FAR 0xc */
 /* enum: XFI Far. */
-/*               MC_CMD_LOOPBACK_XFI_FAR  0xd */
+/*               MC_CMD_LOOPBACK_XFI_FAR 0xd */
 /* enum: GPhy. */
-/*               MC_CMD_LOOPBACK_GPHY  0xe */
+/*               MC_CMD_LOOPBACK_GPHY 0xe */
 /* enum: PhyXS. */
-/*               MC_CMD_LOOPBACK_PHYXS  0xf */
+/*               MC_CMD_LOOPBACK_PHYXS 0xf */
 /* enum: PCS. */
-/*               MC_CMD_LOOPBACK_PCS  0x10 */
+/*               MC_CMD_LOOPBACK_PCS 0x10 */
 /* enum: PMA-PMD. */
-/*               MC_CMD_LOOPBACK_PMAPMD  0x11 */
+/*               MC_CMD_LOOPBACK_PMAPMD 0x11 */
 /* enum: Cross-Port. */
-/*               MC_CMD_LOOPBACK_XPORT  0x12 */
+/*               MC_CMD_LOOPBACK_XPORT 0x12 */
 /* enum: XGMII-Wireside. */
-/*               MC_CMD_LOOPBACK_XGMII_WS  0x13 */
+/*               MC_CMD_LOOPBACK_XGMII_WS 0x13 */
 /* enum: XAUI Wireside. */
-/*               MC_CMD_LOOPBACK_XAUI_WS  0x14 */
+/*               MC_CMD_LOOPBACK_XAUI_WS 0x14 */
 /* enum: XAUI Wireside Far. */
-/*               MC_CMD_LOOPBACK_XAUI_WS_FAR  0x15 */
+/*               MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
 /* enum: XAUI Wireside near. */
-/*               MC_CMD_LOOPBACK_XAUI_WS_NEAR  0x16 */
+/*               MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
 /* enum: GMII Wireside. */
-/*               MC_CMD_LOOPBACK_GMII_WS  0x17 */
+/*               MC_CMD_LOOPBACK_GMII_WS 0x17 */
 /* enum: XFI Wireside. */
-/*               MC_CMD_LOOPBACK_XFI_WS  0x18 */
+/*               MC_CMD_LOOPBACK_XFI_WS 0x18 */
 /* enum: XFI Wireside Far. */
-/*               MC_CMD_LOOPBACK_XFI_WS_FAR  0x19 */
+/*               MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
 /* enum: PhyXS Wireside. */
-/*               MC_CMD_LOOPBACK_PHYXS_WS  0x1a */
+/*               MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
 /* enum: PMA lanes MAC-Serdes. */
-/*               MC_CMD_LOOPBACK_PMA_INT  0x1b */
+/*               MC_CMD_LOOPBACK_PMA_INT 0x1b */
 /* enum: KR Serdes Parallel (Encoder). */
-/*               MC_CMD_LOOPBACK_SD_NEAR  0x1c */
+/*               MC_CMD_LOOPBACK_SD_NEAR 0x1c */
 /* enum: KR Serdes Serial. */
-/*               MC_CMD_LOOPBACK_SD_FAR  0x1d */
+/*               MC_CMD_LOOPBACK_SD_FAR 0x1d */
 /* enum: PMA lanes MAC-Serdes Wireside. */
-/*               MC_CMD_LOOPBACK_PMA_INT_WS  0x1e */
+/*               MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
 /* enum: KR Serdes Parallel Wireside (Full PCS). */
-/*               MC_CMD_LOOPBACK_SD_FEP2_WS  0x1f */
+/*               MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
-/*               MC_CMD_LOOPBACK_SD_FEP1_5_WS  0x20 */
+/*               MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
-/*               MC_CMD_LOOPBACK_SD_FEP_WS  0x21 */
+/*               MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
 /* enum: KR Serdes Serial Wireside. */
-/*               MC_CMD_LOOPBACK_SD_FES_WS  0x22 */
+/*               MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
 /* enum: Near side of AOE Siena side port */
-/*               MC_CMD_LOOPBACK_AOE_INT_NEAR  0x23 */
+/*               MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
 /* enum: Medford Wireside datapath loopback */
-/*               MC_CMD_LOOPBACK_DATA_WS  0x24 */
+/*               MC_CMD_LOOPBACK_DATA_WS 0x24 */
 /* enum: Force link up without setting up any physical loopback (snapper use
  * only)
  */
-/*               MC_CMD_LOOPBACK_FORCE_EXT_LINK  0x25 */
+/*               MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
 /* Supported loopbacks. */
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
 #define	MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
@@ -3701,9 +3737,9 @@
 /* Set LED state. */
 #define	MC_CMD_SET_ID_LED_IN_STATE_OFST 0
 #define	MC_CMD_SET_ID_LED_IN_STATE_LEN 4
-#define	MC_CMD_LED_OFF  0x0 /* enum */
-#define	MC_CMD_LED_ON  0x1 /* enum */
-#define	MC_CMD_LED_DEFAULT  0x2 /* enum */
+#define	MC_CMD_LED_OFF 0x0 /* enum */
+#define	MC_CMD_LED_ON 0x1 /* enum */
+#define	MC_CMD_LED_DEFAULT 0x2 /* enum */
 
 /* MC_CMD_SET_ID_LED_OUT msgresponse */
 #define	MC_CMD_SET_ID_LED_OUT_LEN 0
@@ -3855,53 +3891,53 @@
 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
 #define	MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
 /* enum: OUI. */
-#define	MC_CMD_OUI  0x0
+#define	MC_CMD_OUI 0x0
 /* enum: PMA-PMD Link Up. */
-#define	MC_CMD_PMA_PMD_LINK_UP  0x1
+#define	MC_CMD_PMA_PMD_LINK_UP 0x1
 /* enum: PMA-PMD RX Fault. */
-#define	MC_CMD_PMA_PMD_RX_FAULT  0x2
+#define	MC_CMD_PMA_PMD_RX_FAULT 0x2
 /* enum: PMA-PMD TX Fault. */
-#define	MC_CMD_PMA_PMD_TX_FAULT  0x3
+#define	MC_CMD_PMA_PMD_TX_FAULT 0x3
 /* enum: PMA-PMD Signal */
-#define	MC_CMD_PMA_PMD_SIGNAL  0x4
+#define	MC_CMD_PMA_PMD_SIGNAL 0x4
 /* enum: PMA-PMD SNR A. */
-#define	MC_CMD_PMA_PMD_SNR_A  0x5
+#define	MC_CMD_PMA_PMD_SNR_A 0x5
 /* enum: PMA-PMD SNR B. */
-#define	MC_CMD_PMA_PMD_SNR_B  0x6
+#define	MC_CMD_PMA_PMD_SNR_B 0x6
 /* enum: PMA-PMD SNR C. */
-#define	MC_CMD_PMA_PMD_SNR_C  0x7
+#define	MC_CMD_PMA_PMD_SNR_C 0x7
 /* enum: PMA-PMD SNR D. */
-#define	MC_CMD_PMA_PMD_SNR_D  0x8
+#define	MC_CMD_PMA_PMD_SNR_D 0x8
 /* enum: PCS Link Up. */
-#define	MC_CMD_PCS_LINK_UP  0x9
+#define	MC_CMD_PCS_LINK_UP 0x9
 /* enum: PCS RX Fault. */
-#define	MC_CMD_PCS_RX_FAULT  0xa
+#define	MC_CMD_PCS_RX_FAULT 0xa
 /* enum: PCS TX Fault. */
-#define	MC_CMD_PCS_TX_FAULT  0xb
+#define	MC_CMD_PCS_TX_FAULT 0xb
 /* enum: PCS BER. */
-#define	MC_CMD_PCS_BER  0xc
+#define	MC_CMD_PCS_BER 0xc
 /* enum: PCS Block Errors. */
-#define	MC_CMD_PCS_BLOCK_ERRORS  0xd
+#define	MC_CMD_PCS_BLOCK_ERRORS 0xd
 /* enum: PhyXS Link Up. */
-#define	MC_CMD_PHYXS_LINK_UP  0xe
+#define	MC_CMD_PHYXS_LINK_UP 0xe
 /* enum: PhyXS RX Fault. */
-#define	MC_CMD_PHYXS_RX_FAULT  0xf
+#define	MC_CMD_PHYXS_RX_FAULT 0xf
 /* enum: PhyXS TX Fault. */
-#define	MC_CMD_PHYXS_TX_FAULT  0x10
+#define	MC_CMD_PHYXS_TX_FAULT 0x10
 /* enum: PhyXS Align. */
-#define	MC_CMD_PHYXS_ALIGN  0x11
+#define	MC_CMD_PHYXS_ALIGN 0x11
 /* enum: PhyXS Sync. */
-#define	MC_CMD_PHYXS_SYNC  0x12
+#define	MC_CMD_PHYXS_SYNC 0x12
 /* enum: AN link-up. */
-#define	MC_CMD_AN_LINK_UP  0x13
+#define	MC_CMD_AN_LINK_UP 0x13
 /* enum: AN Complete. */
-#define	MC_CMD_AN_COMPLETE  0x14
+#define	MC_CMD_AN_COMPLETE 0x14
 /* enum: AN 10GBaseT Status. */
-#define	MC_CMD_AN_10GBT_STATUS  0x15
+#define	MC_CMD_AN_10GBT_STATUS 0x15
 /* enum: Clause 22 Link-Up. */
-#define	MC_CMD_CL22_LINK_UP  0x16
+#define	MC_CMD_CL22_LINK_UP 0x16
 /* enum: (Last entry) */
-#define	MC_CMD_PHY_NSTATS  0x17
+#define	MC_CMD_PHY_NSTATS 0x17
 
 
 /***********************************/
@@ -3964,139 +4000,139 @@
 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
 #define	MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
-#define	MC_CMD_MAC_GENERATION_START  0x0 /* enum */
-#define	MC_CMD_MAC_DMABUF_START  0x1 /* enum */
-#define	MC_CMD_MAC_TX_PKTS  0x1 /* enum */
-#define	MC_CMD_MAC_TX_PAUSE_PKTS  0x2 /* enum */
-#define	MC_CMD_MAC_TX_CONTROL_PKTS  0x3 /* enum */
-#define	MC_CMD_MAC_TX_UNICAST_PKTS  0x4 /* enum */
-#define	MC_CMD_MAC_TX_MULTICAST_PKTS  0x5 /* enum */
-#define	MC_CMD_MAC_TX_BROADCAST_PKTS  0x6 /* enum */
-#define	MC_CMD_MAC_TX_BYTES  0x7 /* enum */
-#define	MC_CMD_MAC_TX_BAD_BYTES  0x8 /* enum */
-#define	MC_CMD_MAC_TX_LT64_PKTS  0x9 /* enum */
-#define	MC_CMD_MAC_TX_64_PKTS  0xa /* enum */
-#define	MC_CMD_MAC_TX_65_TO_127_PKTS  0xb /* enum */
-#define	MC_CMD_MAC_TX_128_TO_255_PKTS  0xc /* enum */
-#define	MC_CMD_MAC_TX_256_TO_511_PKTS  0xd /* enum */
-#define	MC_CMD_MAC_TX_512_TO_1023_PKTS  0xe /* enum */
-#define	MC_CMD_MAC_TX_1024_TO_15XX_PKTS  0xf /* enum */
-#define	MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS  0x10 /* enum */
-#define	MC_CMD_MAC_TX_GTJUMBO_PKTS  0x11 /* enum */
-#define	MC_CMD_MAC_TX_BAD_FCS_PKTS  0x12 /* enum */
-#define	MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS  0x13 /* enum */
-#define	MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS  0x14 /* enum */
-#define	MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS  0x15 /* enum */
-#define	MC_CMD_MAC_TX_LATE_COLLISION_PKTS  0x16 /* enum */
-#define	MC_CMD_MAC_TX_DEFERRED_PKTS  0x17 /* enum */
-#define	MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS  0x18 /* enum */
-#define	MC_CMD_MAC_TX_NON_TCPUDP_PKTS  0x19 /* enum */
-#define	MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS  0x1a /* enum */
-#define	MC_CMD_MAC_TX_IP_SRC_ERR_PKTS  0x1b /* enum */
-#define	MC_CMD_MAC_RX_PKTS  0x1c /* enum */
-#define	MC_CMD_MAC_RX_PAUSE_PKTS  0x1d /* enum */
-#define	MC_CMD_MAC_RX_GOOD_PKTS  0x1e /* enum */
-#define	MC_CMD_MAC_RX_CONTROL_PKTS  0x1f /* enum */
-#define	MC_CMD_MAC_RX_UNICAST_PKTS  0x20 /* enum */
-#define	MC_CMD_MAC_RX_MULTICAST_PKTS  0x21 /* enum */
-#define	MC_CMD_MAC_RX_BROADCAST_PKTS  0x22 /* enum */
-#define	MC_CMD_MAC_RX_BYTES  0x23 /* enum */
-#define	MC_CMD_MAC_RX_BAD_BYTES  0x24 /* enum */
-#define	MC_CMD_MAC_RX_64_PKTS  0x25 /* enum */
-#define	MC_CMD_MAC_RX_65_TO_127_PKTS  0x26 /* enum */
-#define	MC_CMD_MAC_RX_128_TO_255_PKTS  0x27 /* enum */
-#define	MC_CMD_MAC_RX_256_TO_511_PKTS  0x28 /* enum */
-#define	MC_CMD_MAC_RX_512_TO_1023_PKTS  0x29 /* enum */
-#define	MC_CMD_MAC_RX_1024_TO_15XX_PKTS  0x2a /* enum */
-#define	MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS  0x2b /* enum */
-#define	MC_CMD_MAC_RX_GTJUMBO_PKTS  0x2c /* enum */
-#define	MC_CMD_MAC_RX_UNDERSIZE_PKTS  0x2d /* enum */
-#define	MC_CMD_MAC_RX_BAD_FCS_PKTS  0x2e /* enum */
-#define	MC_CMD_MAC_RX_OVERFLOW_PKTS  0x2f /* enum */
-#define	MC_CMD_MAC_RX_FALSE_CARRIER_PKTS  0x30 /* enum */
-#define	MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS  0x31 /* enum */
-#define	MC_CMD_MAC_RX_ALIGN_ERROR_PKTS  0x32 /* enum */
-#define	MC_CMD_MAC_RX_LENGTH_ERROR_PKTS  0x33 /* enum */
-#define	MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS  0x34 /* enum */
-#define	MC_CMD_MAC_RX_JABBER_PKTS  0x35 /* enum */
-#define	MC_CMD_MAC_RX_NODESC_DROPS  0x36 /* enum */
-#define	MC_CMD_MAC_RX_LANES01_CHAR_ERR  0x37 /* enum */
-#define	MC_CMD_MAC_RX_LANES23_CHAR_ERR  0x38 /* enum */
-#define	MC_CMD_MAC_RX_LANES01_DISP_ERR  0x39 /* enum */
-#define	MC_CMD_MAC_RX_LANES23_DISP_ERR  0x3a /* enum */
-#define	MC_CMD_MAC_RX_MATCH_FAULT  0x3b /* enum */
+#define	MC_CMD_MAC_GENERATION_START 0x0 /* enum */
+#define	MC_CMD_MAC_DMABUF_START 0x1 /* enum */
+#define	MC_CMD_MAC_TX_PKTS 0x1 /* enum */
+#define	MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
+#define	MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
+#define	MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
+#define	MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
+#define	MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
+#define	MC_CMD_MAC_TX_BYTES 0x7 /* enum */
+#define	MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
+#define	MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
+#define	MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
+#define	MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
+#define	MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
+#define	MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
+#define	MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
+#define	MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
+#define	MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
+#define	MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
+#define	MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
+#define	MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
+#define	MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
+#define	MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
+#define	MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
+#define	MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
+#define	MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
+#define	MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
+#define	MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
+#define	MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
+#define	MC_CMD_MAC_RX_PKTS 0x1c /* enum */
+#define	MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
+#define	MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
+#define	MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
+#define	MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
+#define	MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
+#define	MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
+#define	MC_CMD_MAC_RX_BYTES 0x23 /* enum */
+#define	MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
+#define	MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
+#define	MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
+#define	MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
+#define	MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
+#define	MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
+#define	MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
+#define	MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
+#define	MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
+#define	MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
+#define	MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
+#define	MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
+#define	MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
+#define	MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
+#define	MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
+#define	MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
+#define	MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
+#define	MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
+#define	MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
+#define	MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
+#define	MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
+#define	MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
+#define	MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
+#define	MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
  * capability only.
  */
-#define	MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW  0x3c
+#define	MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
  * PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW  0x3d
+#define	MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
  * capability only.
  */
-#define	MC_CMD_MAC_PM_TRUNC_VFIFO_FULL  0x3e
+#define	MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
  * PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_PM_DISCARD_VFIFO_FULL  0x3f
+#define	MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
  * capability only.
  */
-#define	MC_CMD_MAC_PM_TRUNC_QBB  0x40
+#define	MC_CMD_MAC_PM_TRUNC_QBB 0x40
 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
  * capability only.
  */
-#define	MC_CMD_MAC_PM_DISCARD_QBB  0x41
+#define	MC_CMD_MAC_PM_DISCARD_QBB 0x41
 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
  * capability only.
  */
-#define	MC_CMD_MAC_PM_DISCARD_MAPPING  0x42
+#define	MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
 /* enum: RXDP counter: Number of packets dropped due to the queue being
  * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_RXDP_Q_DISABLED_PKTS  0x43
+#define	MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
  * with PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_RXDP_DI_DROPPED_PKTS  0x45
+#define	MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
  * PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_RXDP_STREAMING_PKTS  0x46
+#define	MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
  * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS  0x47
+#define	MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
  * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
  */
-#define	MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS  0x48
-#define	MC_CMD_MAC_VADAPTER_RX_DMABUF_START  0x4c /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS  0x4c /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES  0x4d /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS  0x4e /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES  0x4f /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS  0x50 /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES  0x51 /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS  0x52 /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_BAD_BYTES  0x53 /* enum */
-#define	MC_CMD_MAC_VADAPTER_RX_OVERFLOW  0x54 /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_DMABUF_START  0x57 /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS  0x57 /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES  0x58 /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS  0x59 /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES  0x5a /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS  0x5b /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES  0x5c /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS  0x5d /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_BAD_BYTES  0x5e /* enum */
-#define	MC_CMD_MAC_VADAPTER_TX_OVERFLOW  0x5f /* enum */
+#define	MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
+#define	MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
+#define	MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
+#define	MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
 /* enum: Start of GMAC stats buffer space, for Siena only. */
-#define	MC_CMD_GMAC_DMABUF_START  0x40
+#define	MC_CMD_GMAC_DMABUF_START 0x40
 /* enum: End of GMAC stats buffer space, for Siena only. */
-#define	MC_CMD_GMAC_DMABUF_END    0x5f
+#define	MC_CMD_GMAC_DMABUF_END 0x5f
 /* enum: GENERATION_END value, used together with GENERATION_START to verify
  * consistency of DMAd data. For legacy firmware / drivers without extended
  * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
@@ -4108,7 +4144,7 @@
  * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
  */
 #define	MC_CMD_MAC_GENERATION_END 0x60
-#define	MC_CMD_MAC_NSTATS  0x61 /* enum */
+#define	MC_CMD_MAC_NSTATS 0x61 /* enum */
 
 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
 #define	MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
@@ -4121,25 +4157,25 @@
 #define	MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
 #define	MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
 /* enum: Start of FEC stats buffer space, Medford2 and up */
-#define	MC_CMD_MAC_FEC_DMABUF_START  0x61
+#define	MC_CMD_MAC_FEC_DMABUF_START 0x61
 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
  */
-#define	MC_CMD_MAC_FEC_UNCORRECTED_ERRORS  0x61
+#define	MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
  */
-#define	MC_CMD_MAC_FEC_CORRECTED_ERRORS  0x62
+#define	MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
-#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0  0x63
+#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
-#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1  0x64
+#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
-#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2  0x65
+#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
-#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3  0x66
+#define	MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
 /* enum: This includes the space at offset 103 which is the final
  * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
  */
-#define	MC_CMD_MAC_NSTATS_V2  0x68
+#define	MC_CMD_MAC_NSTATS_V2 0x68
 /*            Other enum values, see field(s): */
 /*               MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
 
@@ -4154,66 +4190,66 @@
 #define	MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
 #define	MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
 /* enum: Start of CTPIO stats buffer space, Medford2 and up */
-#define	MC_CMD_MAC_CTPIO_DMABUF_START  0x68
+#define	MC_CMD_MAC_CTPIO_DMABUF_START 0x68
 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
  * target VI
  */
-#define	MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK  0x68
+#define	MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
 /* enum: Number of times a CTPIO send wrote beyond frame end (informational
  * only)
  */
-#define	MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS  0x69
+#define	MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
 /* enum: Number of CTPIO failures because the TX doorbell was written before
  * the end of the frame data
  */
-#define	MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL  0x6a
+#define	MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
 /* enum: Number of CTPIO failures because the internal FIFO overflowed */
-#define	MC_CMD_MAC_CTPIO_OVERFLOW_FAIL  0x6b
+#define	MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
 /* enum: Number of CTPIO failures because the host did not deliver data fast
  * enough to avoid MAC underflow
  */
-#define	MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL  0x6c
+#define	MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
 /* enum: Number of CTPIO failures because the host did not deliver all the
  * frame data within the timeout
  */
-#define	MC_CMD_MAC_CTPIO_TIMEOUT_FAIL  0x6d
+#define	MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
 /* enum: Number of CTPIO failures because the frame data arrived out of order
  * or with gaps
  */
-#define	MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL  0x6e
+#define	MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
 /* enum: Number of CTPIO failures because the host started a new frame before
  * completing the previous one
  */
-#define	MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL  0x6f
+#define	MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
  * or not 32-bit aligned
  */
-#define	MC_CMD_MAC_CTPIO_INVALID_WR_FAIL  0x70
+#define	MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
 /* enum: Number of CTPIO fallbacks because another VI on the same port was
  * sending a CTPIO frame
  */
-#define	MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK  0x71
+#define	MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
  */
-#define	MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK  0x72
+#define	MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
 /* enum: Number of CTPIO fallbacks because length in header was less than 29
  * bytes
  */
-#define	MC_CMD_MAC_CTPIO_RUNT_FALLBACK  0x73
+#define	MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
 /* enum: Total number of successful CTPIO sends on this port */
-#define	MC_CMD_MAC_CTPIO_SUCCESS  0x74
+#define	MC_CMD_MAC_CTPIO_SUCCESS 0x74
 /* enum: Total number of CTPIO fallbacks on this port */
-#define	MC_CMD_MAC_CTPIO_FALLBACK  0x75
+#define	MC_CMD_MAC_CTPIO_FALLBACK 0x75
 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or
  * not
  */
-#define	MC_CMD_MAC_CTPIO_POISON  0x76
+#define	MC_CMD_MAC_CTPIO_POISON 0x76
 /* enum: Total number of CTPIO erased frames on this port */
-#define	MC_CMD_MAC_CTPIO_ERASE  0x77
+#define	MC_CMD_MAC_CTPIO_ERASE 0x77
 /* enum: This includes the space at offset 120 which is the final
  * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
  */
-#define	MC_CMD_MAC_NSTATS_V3  0x79
+#define	MC_CMD_MAC_NSTATS_V3 0x79
 /*            Other enum values, see field(s): */
 /*               MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
 
@@ -4323,25 +4359,25 @@
 #define	MC_CMD_WOL_FILTER_SET_IN_LEN 192
 #define	MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
 #define	MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
-#define	MC_CMD_FILTER_MODE_SIMPLE    0x0 /* enum */
+#define	MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
 #define	MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
 /* A type value of 1 is unused. */
 #define	MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
 #define	MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
 /* enum: Magic */
-#define	MC_CMD_WOL_TYPE_MAGIC      0x0
+#define	MC_CMD_WOL_TYPE_MAGIC 0x0
 /* enum: MS Windows Magic */
 #define	MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
 /* enum: IPv4 Syn */
-#define	MC_CMD_WOL_TYPE_IPV4_SYN   0x3
+#define	MC_CMD_WOL_TYPE_IPV4_SYN 0x3
 /* enum: IPv6 Syn */
-#define	MC_CMD_WOL_TYPE_IPV6_SYN   0x4
+#define	MC_CMD_WOL_TYPE_IPV6_SYN 0x4
 /* enum: Bitmap */
-#define	MC_CMD_WOL_TYPE_BITMAP     0x5
+#define	MC_CMD_WOL_TYPE_BITMAP 0x5
 /* enum: Link */

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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