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Date:      Sat, 15 Feb 2003 11:21:42 -0800
From:      Peter Wemm <peter@wemm.org>
To:        Marcel Moolenaar <marcel@xcllnt.net>
Cc:        Eric Anholt <eta@lclark.edu>, src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   Re: cvs commit: src/sys/modules Makefile 
Message-ID:  <20030215192142.E79BE2A89E@canning.wemm.org>
In-Reply-To: <20030214061708.GA2109@athlon.pn.xcllnt.net> 

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Marcel Moolenaar wrote:
> On Thu, Feb 13, 2003 at 09:32:33PM -0800, Eric Anholt wrote:
> > > 
> > > In that case, we'd better make sure there's cache coherency. Do we
> > > actually have the code structured in a way that allows having the
> > > flushing chipset dependent (not to mention dependent on the address)?
> > 
> > No, currently all the cache flushes (four in agp.c, three in i810 and
> > amd code) are unconditional agp_flush_cache calls after modifying the
> > gatt entries.  They aren't tied to a specific memory range, but could be
> > pretty easily, if not the most efficiently, by pushing some of them into
> > the (un)bind_pages.  There's probably a better way.
> 
> I wonder: do we actually need to flush at all? GART updates are PCI/AGP
> writes and should be coherent, right?

Consider the remap table.  It is external to the cpu, on the far side of
the writeback cache.   Changing remap entries with pending writes would
be interesting.  AGP isn't necessarily coherent either.

> Also, on ia64 bus I/O is done with a virtual address that has the
> non-cacheable property. Flushing would not be required irrespective.

What about user mmaped IO?  eg: when the Xserver has got stuff remapped
down into user memory?  And what if the remap table is changed underneath
that?  On i386, the MTRR stuff is used to control cache behavior so that
the userland portions can be in writeback mode.  I dont recall what happens
on ia64.

I really dont understand this stuff well enough.

Cheers,
-Peter
--
Peter Wemm - peter@wemm.org; peter@FreeBSD.org; peter@yahoo-inc.com
"All of this is for nothing if we don't go to the stars" - JMS/B5


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