Date: Wed, 16 Jul 1997 21:52:30 -0600 From: Steve Passe <smp@csn.net> To: Peter Wemm <peter@spinner.dialix.com.au> Cc: listuser <listuser@h2o.journey.net>, Chuck Robey <chuckr@Glue.umd.edu>, smp@FreeBSD.ORG Subject: Re: HEADS UP: EISA cards. Message-ID: <199707170352.VAA11792@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Thu, 17 Jul 1997 11:36:57 %2B0800." <199707170336.LAA23469@spinner.dialix.com.au>
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Peter, > Again, remember that the feature that we are talking about (DMA Chaining) > ... > purpose of building a high performance system with multiple CPUs anyway. a related aspect of this is the functionality we gain by programming IO APIC pin 0 as a 'regular' INT. Specifically, the 8259 becomes nothing more than a buffer chip for the 8254 timer. It probably delays the clock INT by about 10nsec, but this is probably pretty constant. And the timer returns to being on vec[ 0 ] as a result. We might consider programming ALL systems this way, whether they connect the timer to IO APIC pin 2 or not. This would eliminate the "song and dance" I go thru using the vec[] array and the indirections thru it to get to the hardware resumption routines. This may well be why intel designed the PR440FX board to NOT have an IO APIC pin 2 connection to the timer. -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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