Date: Fri, 29 Feb 2008 19:47:39 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 136413 for review Message-ID: <200802291947.m1TJldWN092279@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=136413 Change 136413 by rrs@rrs-mips2-jnpr on 2008/02/28 09:35:01 make context use pnemonics too. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#18 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#18 (text+ko) ==== @@ -155,14 +155,14 @@ if (td1 == PCPU_GET(fpcurthread)) MipsSaveCurFPState(td1); - pcb2->pcb_context.val[10] = (register_t)fork_trampoline; + pcb2->pcb_context.val[PCB_REG_RA] = (register_t)fork_trampoline; /* Make sp 64-bit aligned */ - pcb2->pcb_context.val[8] = (register_t)(((vm_offset_t)td2->td_pcb & + pcb2->pcb_context.val[PCB_REG_SP] = (register_t)(((vm_offset_t)td2->td_pcb & ~(sizeof(__int64_t) - 1)) - STAND_FRAME_SIZE); - pcb2->pcb_context.val[0] = (register_t)fork_return; - pcb2->pcb_context.val[1] = (register_t)td2; - pcb2->pcb_context.val[2] = (register_t)td2->td_frame; - pcb2->pcb_context.val[11] = SR_INT_MASK; /* SR */ + pcb2->pcb_context.val[PCB_REG_S0] = (register_t)fork_return; + pcb2->pcb_context.val[PCB_REG_S1] = (register_t)td2; + pcb2->pcb_context.val[PCB_REG_S2] = (register_t)td2->td_frame; + pcb2->pcb_context.val[PCB_REG_SR] = SR_INT_MASK; /* SR */ /* * FREEBSD_DEVELOPERS_FIXME: * Setup any other CPU-Specific registers (Not MIPS Standard) @@ -173,7 +173,7 @@ td2->td_md.md_saved_intr = 1; td2->td_md.md_spinlock_count = 1; #ifdef TARGET_OCTEON - pcb2->pcb_context.val[11] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; + pcb2->pcb_context.val[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; #endif } @@ -191,8 +191,8 @@ * Note that the trap frame follows the args, so the function * is really called like this: func(arg, frame); */ - td->td_pcb->pcb_context.val[0] = (register_t) func; - td->td_pcb->pcb_context.val[1] = (register_t) arg; + td->td_pcb->pcb_context.val[PCB_REG_S0] = (register_t) func; + td->td_pcb->pcb_context.val[PCB_REG_S1] = (register_t) arg; } void @@ -305,18 +305,18 @@ * Set registers for trampoline to user mode. */ - pcb2->pcb_context.val[10] = (register_t)fork_trampoline; + pcb2->pcb_context.val[PCB_REG_RA] = (register_t)fork_trampoline; /* Make sp 64-bit aligned */ - pcb2->pcb_context.val[8] = (register_t)(((vm_offset_t)td->td_pcb & + pcb2->pcb_context.val[PCB_REG_SP] = (register_t)(((vm_offset_t)td->td_pcb & ~(sizeof(__int64_t) - 1)) - STAND_FRAME_SIZE); - pcb2->pcb_context.val[0] = (register_t)fork_return; - pcb2->pcb_context.val[1] = (register_t)td; - pcb2->pcb_context.val[2] = (register_t)td->td_frame; + pcb2->pcb_context.val[PCB_REG_S0] = (register_t)fork_return; + pcb2->pcb_context.val[PCB_REG_S1] = (register_t)td; + pcb2->pcb_context.val[PCB_REG_S2] = (register_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ /* idle_mask is jmips pcb2->pcb_context.val[11] = (ALL_INT_MASK & idle_mask); */ - pcb2->pcb_context.val[11] = 0; + pcb2->pcb_context.val[PCB_REG_SR] = 0; #ifdef TARGET_OCTEON - pcb2->pcb_context.val[11] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | + pcb2->pcb_context.val[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX; #endif
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