Date: Sat, 28 Jul 2007 16:03:12 GMT From: Christopher Davis <loafier@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 124268 for review Message-ID: <200707281603.l6SG3CK3048854@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=124268 Change 124268 by loafier@chrisdsoc on 2007/07/28 16:02:31 Edited for bus_alloc_resources(), etc Affected files ... .. //depot/projects/soc2007/loafier_busalloc/src/sys/dev/sound/pci/t4dwave.c#2 edit Differences ... ==== //depot/projects/soc2007/loafier_busalloc/src/sys/dev/sound/pci/t4dwave.c#2 (text+ko) ==== @@ -78,17 +78,26 @@ struct tr_info *parent; }; +enum { + RES_MEM, + RES_IRQ, + RES_SZ +}; + +static struct resource_spec tr_res_spec[] = { + {SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE}, + {SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, + {-1, 0, 0} +}; + /* device private data */ struct tr_info { u_int32_t type; u_int32_t rev; - bus_space_tag_t st; - bus_space_handle_t sh; bus_dma_tag_t parent_dmat; - struct resource *reg, *irq; - int regtype, regid, irqid; + struct resource *res[RES_SZ]; void *ih; struct mtx *lock; @@ -131,38 +140,14 @@ /* -------------------------------------------------------------------- */ /* Hardware */ +#define tr_rd1(_sc, _reg) bus_read_1((_sc)->res[RES_MEM], _reg) +#define tr_rd2(_sc, _reg) bus_read_2((_sc)->res[RES_MEM], _reg) +#define tr_rd4(_sc, _reg) bus_read_4((_sc)->res[RES_MEM], _reg) +#define tr_wr1(_sc, _reg, _val) bus_write_1((_sc)->res[RES_MEM], _reg, _val) +#define tr_wr2(_sc, _reg, _val) bus_write_2((_sc)->res[RES_MEM], _reg, _val) +#define tr_wr4(_sc, _reg, _val) bus_write_4((_sc)->res[RES_MEM], _reg, _val) -static u_int32_t -tr_rd(struct tr_info *tr, int regno, int size) -{ - switch(size) { - case 1: - return bus_space_read_1(tr->st, tr->sh, regno); - case 2: - return bus_space_read_2(tr->st, tr->sh, regno); - case 4: - return bus_space_read_4(tr->st, tr->sh, regno); - default: - return 0xffffffff; - } -} -static void -tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size) -{ - switch(size) { - case 1: - bus_space_write_1(tr->st, tr->sh, regno, data); - break; - case 2: - bus_space_write_2(tr->st, tr->sh, regno, data); - break; - case 4: - bus_space_write_4(tr->st, tr->sh, regno, data); - break; - } -} - /* -------------------------------------------------------------------- */ /* ac97 codec */ @@ -205,20 +190,20 @@ u_int32_t chk1, chk2; j = trw; for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) - j = tr_rd(tr, treg, 4); + j = tr_rd4(tr, treg); if (i > 0) { - chk1 = tr_rd(tr, 0xc8, 4); - chk2 = tr_rd(tr, 0xc8, 4); + chk1 = tr_rd4(tr, 0xc8); + chk2 = tr_rd4(tr, 0xc8); for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); i--) - chk2 = tr_rd(tr, 0xc8, 4); + chk2 = tr_rd4(tr, 0xc8); } } if (tr->type != ALI_PCI_ID || i > 0) { - tr_wr(tr, treg, regno | trw, 4); + tr_wr4(tr, treg, regno | trw); j=trw; for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) - j=tr_rd(tr, treg, 4); + j=tr_rd4(tr, treg); } snd_mtxunlock(tr->lock); if (i == 0) printf("codec timeout during read of register %x\n", regno); @@ -261,22 +246,22 @@ if (tr->type == ALI_PCI_ID) { j = trw; for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) - j = tr_rd(tr, treg, 4); + j = tr_rd4(tr, treg); if (i > 0) { u_int32_t chk1, chk2; - chk1 = tr_rd(tr, 0xc8, 4); - chk2 = tr_rd(tr, 0xc8, 4); + chk1 = tr_rd4(tr, 0xc8); + chk2 = tr_rd4(tr, 0xc8); for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); i--) - chk2 = tr_rd(tr, 0xc8, 4); + chk2 = tr_rd4(tr, 0xc8); } } if (tr->type != ALI_PCI_ID || i > 0) { for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--) - j=tr_rd(tr, treg, 4); + j=tr_rd4(tr, treg); if (tr->type == ALI_PCI_ID && tr->rev > 0x01) trw |= 0x0100; - tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4); + tr_wr4(tr, treg, (data << TR_CDC_DATA) | regno | trw); } #if 0 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno)); @@ -305,7 +290,7 @@ bank = (ch->index & 0x20) ? 1 : 0; chan = ch->index & 0x1f; - return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan); + return tr_rd4(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA) & (1 << chan); } #endif @@ -317,7 +302,7 @@ bank = (ch->index & 0x20) ? 1 : 0; chan = ch->index & 0x1f; - tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4); + tr_wr4(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan); } static void @@ -332,12 +317,12 @@ chan = ch->index & 0x1f; reg = bank? TR_REG_INTENB : TR_REG_INTENA; - i = tr_rd(tr, reg, 4); + i = tr_rd4(tr, reg); i &= ~(1 << chan); i |= (enable? 1 : 0) << chan; tr_clrint(ch); - tr_wr(tr, reg, i, 4); + tr_wr4(tr, reg, i); snd_mtxunlock(tr->lock); } @@ -349,10 +334,10 @@ struct tr_info *tr = ch->parent; int i; - i = tr_rd(tr, TR_REG_CIR, 4); + i = tr_rd4(tr, TR_REG_CIR); i &= ~TR_CIR_MASK; i |= ch->index & 0x3f; - tr_wr(tr, TR_REG_CIR, i, 4); + tr_wr4(tr, TR_REG_CIR, i); } static void @@ -363,7 +348,7 @@ bank = (ch->index & 0x20) ? 1 : 0; chan = ch->index & 0x1f; - tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4); + tr_wr4(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan); } static void @@ -374,7 +359,7 @@ bank = (ch->index & 0x20) ? 1 : 0; chan = ch->index & 0x1f; - tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4); + tr_wr4(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan); } static void @@ -420,7 +405,7 @@ snd_mtxlock(tr->lock); tr_selch(ch); for (i=0; i<TR_CHN_REGS; i++) - tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4); + tr_wr4(tr, TR_REG_CHNBASE+(i<<2), cr[i]); snd_mtxunlock(tr->lock); } @@ -433,7 +418,7 @@ snd_mtxlock(tr->lock); tr_selch(ch); for (i=0; i<5; i++) - cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4); + cr[i]=tr_rd4(tr, TR_REG_CHNBASE+(i<<2)); snd_mtxunlock(tr->lock); @@ -618,10 +603,10 @@ bits = tr_fmttobits(format); /* set # of samples between interrupts */ i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1; - tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4); + tr_wr4(tr, TR_REG_SBBL, i | (i << 16)); /* set sample format */ i = 0x18 | (bits << 4); - tr_wr(tr, TR_REG_SBCTRL, i, 1); + tr_wr1(tr, TR_REG_SBCTRL, i); return 0; @@ -635,7 +620,7 @@ /* setup speed */ ch->delta = (48000 << 12) / speed; - tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2); + tr_wr2(tr, TR_REG_SBDELTA, ch->delta); /* return closest possible speed */ return (48000 << 12) / ch->delta; @@ -663,19 +648,19 @@ if (go == PCMTRIG_START) { /* set up dma mode regs */ - tr_wr(tr, TR_REG_DMAR15, 0, 1); - i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03; - tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1); + tr_wr1(tr, TR_REG_DMAR15, 0); + i = tr_rd1(tr, TR_REG_DMAR11) & 0x03; + tr_wr1(tr, TR_REG_DMAR11, i | 0x54); /* set up base address */ - tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4); + tr_wr4(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer)); /* set up buffer size */ - i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff; - tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4); + i = tr_rd4(tr, TR_REG_DMAR4) & ~0x00ffffff; + tr_wr4(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1)); /* start */ - tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1); + tr_wr1(tr, TR_REG_SBCTRL, tr_rd1(tr, TR_REG_SBCTRL) | 1); ch->active = 1; } else { - tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1); + tr_wr1(tr, TR_REG_SBCTRL, tr_rd1(tr, TR_REG_SBCTRL) & ~7); ch->active = 0; } @@ -690,7 +675,7 @@ struct tr_info *tr = ch->parent; /* return current byte offset of channel */ - return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer); + return tr_rd4(tr, TR_REG_DMAR0) - sndbuf_getbufaddr(ch->buffer); } static struct pcmchan_caps * @@ -722,13 +707,13 @@ u_int32_t active, mask, bufhalf, chnum, intsrc; int tmp; - intsrc = tr_rd(tr, TR_REG_MISCINT, 4); + intsrc = tr_rd4(tr, TR_REG_MISCINT); if (intsrc & TR_INT_ADDR) { chnum = 0; while (chnum < 64) { mask = 0x00000001; - active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); - bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); + active = tr_rd4(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB); + bufhalf = tr_rd4(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B); if (active) { do { if (active & mask) { @@ -748,13 +733,13 @@ } else chnum += 32; - tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4); + tr_wr4(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active); } } if (intsrc & TR_INT_SB) { chn_intr(tr->recchinfo.channel); - tr_rd(tr, TR_REG_SBR9, 1); - tr_rd(tr, TR_REG_SBR10, 1); + tr_rd1(tr, TR_REG_SBR9); + tr_rd1(tr, TR_REG_SBR10); } } @@ -769,21 +754,34 @@ { switch (tr->type) { case SPA_PCI_ID: - tr_wr(tr, SPA_REG_GPIO, 0, 4); - tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); + tr_wr4(tr, SPA_REG_GPIO, 0); + tr_wr4(tr, SPA_REG_CODECST, SPA_RST_OFF); break; case TDX_PCI_ID: - tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); + tr_wr4(tr, TDX_REG_CODECST, TDX_CDC_ON); break; case TNX_PCI_ID: - tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4); + tr_wr4(tr, TNX_REG_CODECST, TNX_CDC_ON); break; } - tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4); + tr_wr4(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA); return 0; } +static void +tr_destroy(device_t dev, struct tr_info *tr) +{ + if (!tr) + return; + + if (tr->ih) bus_teardown_intr(dev, tr->res[RES_IRQ], tr->ih); + bus_release_resources(dev, tr_res_spec, tr->res); + if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); + if (tr->lock) snd_mtxfree(tr->lock); + free(tr, M_DEVBUF); +} + static int tr_pci_probe(device_t dev) { @@ -808,7 +806,6 @@ static int tr_pci_attach(device_t dev) { - u_int32_t data; struct tr_info *tr; struct ac97_info *codec = 0; int i; @@ -819,20 +816,11 @@ tr->rev = pci_get_revid(dev); tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc"); - data = pci_read_config(dev, PCIR_COMMAND, 2); - data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); - pci_write_config(dev, PCIR_COMMAND, data, 2); - data = pci_read_config(dev, PCIR_COMMAND, 2); + pci_enable_busmaster(dev); + pci_enable_io(dev, SYS_RES_IOPORT); - tr->regid = PCIR_BAR(0); - tr->regtype = SYS_RES_IOPORT; - tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid, - RF_ACTIVE); - if (tr->reg) { - tr->st = rman_get_bustag(tr->reg); - tr->sh = rman_get_bushandle(tr->reg); - } else { - device_printf(dev, "unable to map register space\n"); + if (bus_alloc_resources(dev, tr_res_spec, tr->res) != 0) { + device_printf(dev, "unable to allocate resources\n"); goto bad; } @@ -848,10 +836,7 @@ if (codec == NULL) goto bad; if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; - tr->irqid = 0; - tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid, - RF_ACTIVE | RF_SHAREABLE); - if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) { + if (snd_setup_intr(dev, tr->res[RES_IRQ], 0, tr_intr, tr, &tr->ih)) { device_printf(dev, "unable to map interrupt\n"); goto bad; } @@ -869,7 +854,9 @@ } snprintf(status, 64, "at io 0x%lx irq %ld %s", - rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave)); + rman_get_start(tr->res[RES_MEM]), + rman_get_start(tr->res[RES_IRQ]), + PCM_KLDSTRING(snd_t4dwave)); if (pcm_register(dev, tr, TR_MAXPLAYCH, 1)) goto bad; pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr); @@ -881,12 +868,8 @@ bad: if (codec) ac97_destroy(codec); - if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); - if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih); - if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); - if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); - if (tr->lock) snd_mtxfree(tr->lock); - free(tr, M_DEVBUF); + tr_destroy(dev, tr); + return ENXIO; } @@ -901,12 +884,7 @@ return r; tr = pcm_getdevinfo(dev); - bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); - bus_teardown_intr(dev, tr->irq, tr->ih); - bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); - bus_dma_tag_destroy(tr->parent_dmat); - snd_mtxfree(tr->lock); - free(tr, M_DEVBUF); + tr_destroy(dev, tr); return 0; }
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