Date: Thu, 23 May 2019 23:37:11 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r348210 - in head/sys: amd64/amd64 x86/include Message-ID: <201905232337.x4NNbBQ5035096@repo.freebsd.org>
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Author: jhb Date: Thu May 23 23:37:11 2019 New Revision: 348210 URL: https://svnweb.freebsd.org/changeset/base/348210 Log: Add a constant for the LS config MSR on AMD CPUs. MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D19506 Modified: head/sys/amd64/amd64/initcpu.c head/sys/x86/include/specialreg.h Modified: head/sys/amd64/amd64/initcpu.c ============================================================================== --- head/sys/amd64/amd64/initcpu.c Thu May 23 23:06:26 2019 (r348209) +++ head/sys/amd64/amd64/initcpu.c Thu May 23 23:37:11 2019 (r348210) @@ -124,9 +124,9 @@ init_amd(void) */ if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { if ((cpu_feature2 & CPUID2_HV) == 0) { - msr = rdmsr(0xc0011020); + msr = rdmsr(MSR_LS_CFG); msr |= (uint64_t)1 << 15; - wrmsr(0xc0011020, msr); + wrmsr(MSR_LS_CFG, msr); } } @@ -139,9 +139,9 @@ init_amd(void) wrmsr(0xc0011029, msr); /* 1033 */ - msr = rdmsr(0xc0011020); + msr = rdmsr(MSR_LS_CFG); msr |= 0x10; - wrmsr(0xc0011020, msr); + wrmsr(MSR_LS_CFG, msr); /* 1049 */ msr = rdmsr(0xc0011028); @@ -149,9 +149,9 @@ init_amd(void) wrmsr(0xc0011028, msr); /* 1095 */ - msr = rdmsr(0xc0011020); + msr = rdmsr(MSR_LS_CFG); msr |= 0x200000000000000; - wrmsr(0xc0011020, msr); + wrmsr(MSR_LS_CFG, msr); } /* Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Thu May 23 23:06:26 2019 (r348209) +++ head/sys/x86/include/specialreg.h Thu May 23 23:37:11 2019 (r348210) @@ -1098,6 +1098,7 @@ #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ +#define MSR_LS_CFG 0xc0011020 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ /* MSR_VM_CR related */
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