Date: Sat, 30 Jun 2018 19:55:08 +0300 From: Konstantin Belousov <kostikbel@gmail.com> To: Pete French <petefrench@ingresso.co.uk> Cc: avg@freebsd.org, eric@vangyzen.net, freebsd-stable@freebsd.org, freebsd@hda3.com, mike@sentex.net, truckman@FreeBSD.org Subject: Re: Ryzen issues on FreeBSD ? (with sort of workaround) Message-ID: <20180630165508.GT2430@kib.kiev.ua> In-Reply-To: <E1fXn8b-0000se-1B@dilbert.ingresso.co.uk> References: <20180626112919.GK2430@kib.kiev.ua> <E1fXn8b-0000se-1B@dilbert.ingresso.co.uk>
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On Tue, Jun 26, 2018 at 01:32:01PM +0100, Pete French wrote:
> the dmesg wraps around if I boot verbosely, but heres the contnets of
> /var/log/messages from the time it starts to where it stops
> talking about CPU specific stuff... if you need something else then
> let me know - this is an easy machine to reboot and play about with.
This should be the kernel patch equivalent to the script.
According to the revision document, some of the erratas are applicable
to the Ryzen 2, but I do not want to do the bit tweaking without a
confirmation.
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index ccc5e64d0c4..aac3ccb7c73 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -130,6 +130,29 @@ init_amd(void)
}
}
+ /* Ryzen erratas. */
+ if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
+ /* 1021 */
+ msr = rdmsr(0xc0011029);
+ msr |= 0x2000;
+ wrmsr(0xc0011029, msr);
+
+ /* 1033 */
+ msr = rdmsr(0xc0011020);
+ msr |= 0x10;
+ wrmsr(0xc0011020, msr);
+
+ /* 1049 */
+ msr = rdmsr(0xc0011028);
+ msr |= 0x10;
+ wrmsr(0xc0011028, msr);
+
+ /* 1095 */
+ msr = rdmsr(0xc0011020);
+ msr |= 0x200000000000000;
+ wrmsr(0xc0011020, msr);
+ }
+
/*
* Work around a problem on Ryzen that is triggered by executing
* code near the top of user memory, in our case the signal
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index 0ea6e61e652..c3900dadf05 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -998,18 +998,18 @@
#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
+#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
+#define MSR_MC0_CTL_MASK 0xc0010044
#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
+#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
+#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
-#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
-#define MSR_MC0_CTL_MASK 0xc0010044
-#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
-#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
/* MSR_VM_CR related */
#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
diff --git a/sys/x86/x86/cpu_machdep.c b/sys/x86/x86/cpu_machdep.c
index d897d518cbc..3416f949686 100644
--- a/sys/x86/x86/cpu_machdep.c
+++ b/sys/x86/x86/cpu_machdep.c
@@ -709,6 +709,13 @@ cpu_idle_tun(void *unused __unused)
if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
cpu_idle_selector(tunvar);
+ else if (cpu_vendor_id == CPU_VENDOR_AMD &&
+ CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
+ /* Ryzen erratas 1057, 1109. */
+ cpu_idle_selector("hlt");
+ idle_mwait = 0;
+ }
+
if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
/*
* Apollo Lake errata APL31 (public errata APL30).
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