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Date:      Tue, 12 May 1998 18:21:13 +0000 (GMT)
From:      Terry Lambert <tlambert@primenet.com>
To:        dg@root.com
Cc:        steve@visint.co.uk, tlambert@primenet.com, freebsd-current@FreeBSD.ORG
Subject:   Re: Intel Etherexpress PRO/100+ PCI
Message-ID:  <199805121821.LAA23722@usr04.primenet.com>
In-Reply-To: <199805121212.FAA23850@implode.root.com> from "David Greenman" at May 12, 98 05:12:58 am

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> >% I find it unlikely that they are both on INT a.  This may be a bug in
> >% the probe routines, or in your motherboard BIOS.  It could also account
> >% for the start IRQ (say one was on 'INT b', but it wasn't seen).
> >
> >I think this is possibly probe related, although I can't be sure, but I've
> >just checked another six machines none of which use are probed as using
> >anything but int A.
> 
>    Terry just doesn't understand how interrupts work on the PCI bus, despite
> providing a nice picture. :-) All of the PCI cards with a single interrupt
> will use INT A - that's just how it works and is the reason for the interrupts
> being cascaded the way they are on the bus. INT A on one slot is not the same
> interrupt on another.

???

Uh, that's what I said.

I think it's unlikely that cards in two different slots will have INT a
assigned to them, unless the bus lines are *not* cascaded, which I also
think is unlikely on a modern motherboard.

Why are both cards reported on INT a?


>    That's not your goal. You want them to each use a different _irq_ not
> a different INT letter. ...but none of this matters because it's not what
> is causing your problem. :-)

Well, you want them to use a different PCI input line, of which there
are four on most chipsets not manufactured by DEC or Apple, and which
are lettered a through d.

Are we asking the card where it thinks it is?  If so, how are we getting
the INT b's from slot 2 to the interrupt handler?

I think it's more useful to report the ID seen by the handler than
the ID seen by the card, especially for something like a dual channel
Adaptec controller leaching two interrupts (INT a from it's slot, and
INT b from the adjacent slot -- wrapping around at the end of the bus).


Am I just not understanding that what's being reported isn't what's
being set up in the IRQ handler list?  If so, this seems wrong...


					Terry Lambert
					terry@lambert.org
---
Any opinions in this posting are my own and not those of my present
or previous employers.

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