Date: Sun, 02 Nov 2008 22:01:32 +0100 From: Andreas Tobler <andreast-list@fgznet.ch> To: Nathan Whitehorn <nwhitehorn@freebsd.org> Cc: FreeBSD PowerPC ML <freebsd-ppc@freebsd.org> Subject: DFS on PowerBook5,4 Message-ID: <490E152C.30300@fgznet.ch>
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This is a multi-part message in MIME format. --------------020907010407040301010107 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Hi Nathan, I played around with adjusting the CPU speed on my PowerBook5,4. Unfortunately I hang now, means I hang when I boot and I hang with the knowledge on how to go on. Attached the diff I have in my tree. The problem I have, I do not know how and what to tell gpio to do the right thing. At OF prompt I can set set-dfs-high and my PB comes up in full speed, 1.5GHz. Having a look at set-dfs-high: set-dfs-high pvr@ 10 rshift 8003 <> if exit else 5 1 gpio! 1 ms hid1@ 1 1f 9 - lshift andc hid1! then ; ok I see that I have to do something with gpio. But I do not know what and how. The difference from set-dfs-high @ OF level and my implementation attempt is the gpio part which is missing right now. Any hints would be great! TIA, Andreas P.S, The mtspr(SPR_HID1, hid1) call is commented since I already shot an installation with it. --------------020907010407040301010107 Content-Type: text/plain; x-mac-type="0"; x-mac-creator="0"; name="dfs_1.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="dfs_1.diff" Index: include/hid.h =================================================================== RCS file: /home/ncvs/src/sys/powerpc/include/hid.h,v retrieving revision 1.5 diff -u -r1.5 hid.h --- include/hid.h 2 Mar 2008 17:05:57 -0000 1.5 +++ include/hid.h 2 Nov 2008 20:28:44 -0000 @@ -146,4 +146,53 @@ * 7457: XBSEN = Extended BAT Block Size Enable */ +/* HID1 definitions from MPC7450 RISC Microprocessor Family Reference Manual, + Rev. 5 */ + +#define HID1_EMCP 0x80000000 /* Machine check signal enable */ +#define HID1_EBA 0x20000000 /* Enable 60x/MPX bus address parity + checking */ +#define HID1_EBD 0x10000000 /* Enable 60x/MPX bus data parity + checking */ +#define HID1_BCLK 0x08000000 /* CLK_OUT clock type selection */ +#define HID1_ECLK 0x02000000 /* CLK_OUT clock type selection */ +#define HID1_PAR 0x01000000 /* Disable precharge of ARTRY */ +#define HID1_DFS4 0x00800000 /* Dynamic frequency switching (DFS) + divide-by-four mode (note 2) */ +#define HID1_DFS2 0x00400000 /* DFS divide-by-two mode (note 1, 2) */ +#define HID1_PC5 0x00020000 /* PLL config bit5 (read only) (note 2) */ +#define HID1_PC0 0x00010000 /* PLL config bit0 (read only)*/ +#define HID1_PC1 0x00008000 /* PLL config bit1 (read only) */ +#define HID1_PC2 0x00004000 /* PLL config bit2 (read only) */ +#define HID1_PC3 0x00002000 /* PLL config bit3 (read only) */ +#define HID1_PC4 0x00001000 /* PLL config bit4 (read only) */ +#define HID1_SYNCBE 0x00000800 /* ABE broadcast enable for sync, eieio */ +#define HID1_ABE 0x00000400 /* ABE enable for dcbf, dcbst, dcbi, icbi, + tlbie, and tlbsync. */ +#define HID1_BITMASK \ + "\20" \ + "\040EMCP\037res\036EBA\035EBD\034BCLK\033res\032ECLK\031PAR" \ + "\030res\027DFS2\026res\025res\024res\023res\022res\021PC0" \ + "\020PC1\017PC2\016PC3\015PC4\014SYNCBEI\013ABE\012res\011res" \ + "\010res\007res\006res\005res\004res\003res\002res\001res" + +#define HID1_7447A_BITMASK \ + "\20" \ + "\040EMCP\037res\036EBA\035EBD\034BCLK\033res\032ECLK\031PAR" \ + "\030DFS4\027DFS2\026res\025res\024res\023res\022res\021PC0" \ + "\020PC1\017PC2\016PC3\015PC4\014SYNCBEI\013ABE\012res\011res" \ + "\010res\007res\006res\005res\004res\003res\002res\001res" + +#define HID1_7448_BITMASK \ + "\20" \ + "\040EMCP\037res\036EBA\035EBD\034BCLK\033res\032ECLK\031PAR" \ + "\030DFS4\027DFS2\026res\025res\024res\023res\022PC5\021PC0" \ + "\020PC1\017PC2\016PC3\015PC4\014SYNCBEI\013ABE\012res\011res" \ + "\010res\007res\006res\005res\004res\003res\002res\001res" + +/* (1): MPC7447A-specific bit, reserved on MPC7450. + (2): MPC7448-specific bit. +*/ + + #endif /* _POWERPC_HID_H_ */ Index: powerpc/cpu.c =================================================================== RCS file: /home/ncvs/src/sys/powerpc/powerpc/cpu.c,v retrieving revision 1.14 diff -u -r1.14 cpu.c --- powerpc/cpu.c 28 Sep 2008 15:12:43 -0000 1.14 +++ powerpc/cpu.c 2 Nov 2008 20:28:45 -0000 @@ -116,11 +116,11 @@ void cpu_setup(u_int cpuid) { - u_int pvr, maj, min, hid0; + u_int pvr, maj, min, hid0, hid1; uint16_t vers, rev, revfmt; const struct cputab *cp; const char *name; - char *bitmask; + char *bitmask_hid0, *bitmask_hid1; pvr = mfpvr(); vers = pvr >> 16; @@ -168,6 +168,7 @@ } hid0 = mfspr(SPR_HID0); + hid1 = mfspr(SPR_HID1); /* * Configure power-saving mode. @@ -189,8 +190,16 @@ powerpc_pow_enabled = 1; break; - case MPC7448: case MPC7447A: + hid0 |= HID0_SGE | HID0_BTIC; + hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; + /* Select NAP mode. */ + hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); + hid0 |= HID0_NAP | HID0_DPM; + hid1 &= ~HID1_DFS2; /* Run in full speed, correct? */ + powerpc_pow_enabled = 1; + break; + case MPC7448: case MPC7457: case MPC7455: case MPC7450: @@ -232,21 +241,37 @@ } mtspr(SPR_HID0, hid0); + if (vers == MPC7447A) { + __asm __volatile("sync"); + /* mtspr(SPR_HID1, hid1); */ + __asm __volatile("sync; isync"); + DELAY(100000); + hid1 = mfspr(SPR_HID1); + } switch (vers) { case MPC7447A: + bitmask_hid0 = HID0_7450_BITMASK; + bitmask_hid1 = HID1_7447A_BITMASK; + break; case MPC7448: + bitmask_hid0 = HID0_7450_BITMASK; + bitmask_hid1 = HID1_7448_BITMASK; + break; case MPC7450: case MPC7455: case MPC7457: - bitmask = HID0_7450_BITMASK; + bitmask_hid0 = HID0_7450_BITMASK; + bitmask_hid1 = HID1_BITMASK; break; case FSL_E500v1: case FSL_E500v2: - bitmask = HID0_E500_BITMASK; + bitmask_hid0 = HID0_E500_BITMASK; + bitmask_hid1 = HID1_BITMASK; break; default: - bitmask = HID0_BITMASK; + bitmask_hid0 = HID0_BITMASK; + bitmask_hid1 = HID1_BITMASK; break; } @@ -270,15 +295,15 @@ l2cr_config = mfspr(SPR_L2CR); - if (bootverbose) - cpu_print_cacheinfo(cpuid, vers); + cpu_print_cacheinfo(cpuid, vers); break; default: printf("\n"); break; } - printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask); + printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask_hid0); + printf("cpu%d: HID1 %b\n", cpuid, hid1, bitmask_hid1); } void @@ -319,6 +344,7 @@ printf("L3 cache disabled"); printf("\n"); break; + case MPC7447A: case IBM750FX: printf("512KB L2 cache\n"); break; --------------020907010407040301010107--
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