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Date:      Sun, 18 May 2014 03:57:54 +0000 (UTC)
From:      John Baldwin <jhb@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r266391 - head/contrib/binutils/opcodes
Message-ID:  <201405180357.s4I3vsrL050494@svn.freebsd.org>
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Author: jhb
Date: Sun May 18 03:57:54 2014
New Revision: 266391
URL: http://svnweb.freebsd.org/changeset/base/266391

Log:
  Add support for the 'rdseed' instruction.

Modified:
  head/contrib/binutils/opcodes/i386-dis.c
  head/contrib/binutils/opcodes/i386-opc.tbl
  head/contrib/binutils/opcodes/i386-tbl.h

Modified: head/contrib/binutils/opcodes/i386-dis.c
==============================================================================
--- head/contrib/binutils/opcodes/i386-dis.c	Sun May 18 03:50:17 2014	(r266390)
+++ head/contrib/binutils/opcodes/i386-dis.c	Sun May 18 03:57:54 2014	(r266391)
@@ -85,6 +85,7 @@ static void OP_MS (int, int);
 static void OP_XS (int, int);
 static void OP_M (int, int);
 static void OP_VMX (int, int);
+static void OP_VMX2 (int, int);
 static void OP_0fae (int, int);
 static void OP_0f07 (int, int);
 static void NOP_Fixup1 (int, int);
@@ -318,6 +319,7 @@ fetch_data (struct disassemble_info *inf
 #define EMC { OP_EMC, v_mode }
 #define MXC { OP_MXC, 0 }
 #define VM { OP_VMX, q_mode }
+#define VM2 { OP_VMX2, q_mode }
 #define OPSUF { OP_3DNowSuffix, 0 }
 #define OPSIMD { OP_SIMD_Suffix, 0 }
 #define XMM0 { XMM_Fixup, 0 }
@@ -1732,7 +1734,7 @@ static const struct dis386 grps[][8] = {
     { "(bad)",	{ XX } },
     { "(bad)",	{ XX } },
     { "",	{ VM } },		/* See OP_VMX.  */
-    { "vmptrst", { Mq } },
+    { "",	{ VM2 } },		/* See OP_VMX2.  */
   },
   /* GRP11_C6 */
   {
@@ -6467,6 +6469,21 @@ OP_VMX (int bytemode, int sizeflag)
 }
 
 static void
+OP_VMX2 (int bytemode, int sizeflag)
+{
+  if (modrm.mod == 3)
+    {
+      strcpy (obuf, "rdseed");
+      OP_E (v_mode, sizeflag);
+    }
+  else
+    {
+      strcpy (obuf, "vmptrst");
+      OP_M (q_mode, sizeflag);
+    }
+}
+
+static void
 REP_Fixup (int bytemode, int sizeflag)
 {
   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,

Modified: head/contrib/binutils/opcodes/i386-opc.tbl
==============================================================================
--- head/contrib/binutils/opcodes/i386-opc.tbl	Sun May 18 03:50:17 2014	(r266390)
+++ head/contrib/binutils/opcodes/i386-opc.tbl	Sun May 18 03:57:54 2014	(r266391)
@@ -1524,3 +1524,4 @@ pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPC
 
 // Intel Random Number Generator extensions
 rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
+rdseed, 1, 0x0fc7, 0x7, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }

Modified: head/contrib/binutils/opcodes/i386-tbl.h
==============================================================================
--- head/contrib/binutils/opcodes/i386-tbl.h	Sun May 18 03:50:17 2014	(r266390)
+++ head/contrib/binutils/opcodes/i386-tbl.h	Sun May 18 03:57:54 2014	(r266391)
@@ -4391,6 +4391,9 @@ const template i386_optab[] =
   {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
     Modrm|NoSuf,
     { Reg16|Reg32|Reg64 } },
+  {"rdseed", 1, 0x0fc7, 0x7, CpuRdRnd,
+    Modrm|NoSuf,
+    { Reg16|Reg32|Reg64 } },
 
   /* Intel Supervisor Mode Access Prevention extensions */
   {"clac", 0, 0x0f01, 0xca, CpuSMAP,

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