Date: Wed, 11 Feb 2015 23:30:47 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r278606 - head/sys/x86/iommu Message-ID: <201502112330.t1BNUlnX090615@svn.freebsd.org>
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Author: kib Date: Wed Feb 11 23:30:46 2015 New Revision: 278606 URL: https://svnweb.freebsd.org/changeset/base/278606 Log: Registers definitions for the new capabilities from the version 2.4 of VT-d specification. Also add definitions for the interrupt remapping table and IEC. Print new capabilities on boot. although there is no hardware which support it. Sponsored by: The FreeBSD Foundation MFC after: 1 week Modified: head/sys/x86/iommu/intel_drv.c head/sys/x86/iommu/intel_reg.h Modified: head/sys/x86/iommu/intel_drv.c ============================================================================== --- head/sys/x86/iommu/intel_drv.c Wed Feb 11 23:28:28 2015 (r278605) +++ head/sys/x86/iommu/intel_drv.c Wed Feb 11 23:30:46 2015 (r278606) @@ -375,7 +375,7 @@ dmar_print_caps(device_t dev, struct dma caphi = unit->hw_cap >> 32; device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); - printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD"); + printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), @@ -385,8 +385,9 @@ dmar_print_caps(device_t dev, struct dma printf("\n"); ecaphi = unit->hw_ecap >> 32; device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, - "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC"); - printf("%b, ", ecaphi, "\020"); + "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" + "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); + printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), DMAR_ECAP_IRO(unit->hw_ecap)); } Modified: head/sys/x86/iommu/intel_reg.h ============================================================================== --- head/sys/x86/iommu/intel_reg.h Wed Feb 11 23:28:28 2015 (r278605) +++ head/sys/x86/iommu/intel_reg.h Wed Feb 11 23:30:46 2015 (r278606) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2013 The FreeBSD Foundation + * Copyright (c) 2013-2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Konstantin Belousov <kib@FreeBSD.org> @@ -79,6 +79,47 @@ typedef struct dmar_pte { #define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */ #define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */ +typedef struct dmar_irte { + uint64_t irte1; + uint64_t irte2; +} dmar_irte_t; +/* Source Validation Type */ +#define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64)) +#define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64)) +#define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64)) +/* Source-id Qualifier */ +#define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64)) +#define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64)) +#define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64)) +#define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64)) +/* Source Identifier */ +#define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x)) +#define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end)) +/* Destination Id */ +#define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) +#define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) +/* Vector */ +#define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) +#define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ +/* Delivery Mode */ +#define DMAR_IRTE1_DLM_FM (0ULL << 5) +#define DMAR_IRTE1_DLM_LP (1ULL << 5 +#define DMAR_IRTE1_DLM_SMI (2ULL << 5) +#define DMAR_IRTE1_DLM_NMI (4ULL << 5) +#define DMAR_IRTE1_DLM_INIT (5ULL << 5) +#define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) +/* Trigger Mode */ +#define DMAR_IRTE1_TM_EDGE (0ULL << 4) +#define DMAR_IRTE1_TM_LEVEL (1ULL << 4) +/* Redirection Hint */ +#define DMAR_IRTE1_RH_DIRECT (0ULL << 3) +#define DMAR_IRTE1_RH_SELECT (1ULL << 3) +/* Destination Mode */ +#define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2) +#define DMAR_IRTE1_DM_LOGICAL (1ULL << 2) +#define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */ +#define DMAR_IRTE1_P (1ULL) /* Present */ + /* Version register */ #define DMAR_VER_REG 0 #define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf) @@ -86,6 +127,8 @@ typedef struct dmar_pte { /* Capabilities register */ #define DMAR_CAP_REG 0x8 +#define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */ +#define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */ #define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */ #define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */ #define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f)) @@ -120,6 +163,17 @@ typedef struct dmar_pte { /* Extended Capabilities register */ #define DMAR_ECAP_REG 0x10 +#define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */ +#define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */ +#define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */ +#define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */ +#define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */ +#define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */ +#define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */ +#define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */ +#define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */ +#define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ +#define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ #define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) /* Maximum Handle Mask Value */ #define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) @@ -283,6 +337,11 @@ typedef struct dmar_pte { #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ +#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */ +#define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ +#define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ +#define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ + #define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ @@ -326,5 +385,8 @@ typedef struct dmar_pte { /* Interrupt Remapping Table Address register */ #define DMAR_IRTA_REG 0xb8 +#define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode + Enable */ +#define DMAR_IRTA_S_MASK 0xf /* Size Mask */ #endif
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